extrq

Extract Field from Register

EXTRQ xmm1, xmm2

Extracts bit field from register (AMD SSE4a).

Details

Extracts a bit field from the 128-bit xmm1 register using the field length and field position specified in xmm2 bits [13:8] and [5:0] respectively. The extracted field is zero-extended and placed in xmm1; bits not part of the extracted field are zeroed. No EFLAGS are affected; this is an AMD SSE4a extension instruction.

Pseudocode Operation

field_length = xmm2[13:8]
field_pos = xmm2[5:0]
if (field_length == 0) then
  field_length = 64
end if
mask = ((1 << field_length) - 1)
extracted = (xmm1 >> field_pos) & mask
xmm1 = extracted

Example

EXTRQ xmm1, xmm2

Encoding

Binary Layout
66
+0
0F
+1
79
+2
ModRM
+3
 
Format SSE4a
Opcode 66 0F 79 /r
Extension SSE4a

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register

Reference (AMD APM)

Description

Extracts specified bits from the lower 64 bits of the first operand (the destination XMM register). The extracted bits are saved in the least-significant bit positions of the lower quadword of the destination; the remaining bits in the lower quadword of the destination register are cleared to 0. The upper quadword of the destination register is undefined. The portion of the source data being extracted is defined by the bit index and the field length. The bit index defines the least-significant bit of the source operand being extracted. Bits [bit index + length field – 1]:[bit index] are extracted. If the sum of the bit index + length field is greater than 64, the results are undefined. For example, if the bit index is 32 (20h) and the field length is 16 (10h), then the result in the destination register will be source [47:32] in bits 15:0, with zeros in bits 63:16. A value of zero in the field length is defined as a length of 64. If the length field is 0 and the bit index is 0, bits 63:0 of the source are extracted. For any other value of the bit index, the results are undefined. The bit index and field length can be specified as immediate values (second and first immediate operands, respectively, in the case of the three argument version of the instruction), or they can both be specified by fields in an XMM source operand. In the latter case, bits [5:0] of the XMM register specify the number of bits to extract (the field length) and bits [13:8] of the XMM register specify the index of the first bit in the field to extract. The bit index and field length are each six bits in length; other bits of the field are ignored. The diagram below illustrates the operation of this instruction. XMM1 second imm8 first imm8 127 64 63 0 7 5 0 7 5 0 shift right mask to field length XMM1 XMM2 127 64 63 0 127 13 8 5 0 shift right mask to field length