movsd
Move Scalar Double-Precision
Moves a single double (low 64 bits) between XMM/Memory.
Pseudocode Operation
dest[63:0] ← src[63:0]
// dest[127:64] unchangedReference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| F2 0F 10 /r | MOVSD xmm1, xmm2 | A | V/V | SSE2 | Move scalar double precision floating-point value from xmm2 to xmm1 register. |
| F2 0F 10 /r | MOVSD xmm1, m64 | A | V/V | SSE2 | Load scalar double precision floating-point value from m64 to xmm1 register. |
| F2 0F 11 /r | MOVSD xmm1/m64, xmm2 | C | V/V | SSE2 | Move scalar double precision floating-point value from xmm2 register to xmm1/m64. |
| VEX.LIG.F2.0F.WIG 10 /r | VMOVSD xmm1, xmm2, xmm3 | B | V/V | AVX | Merge scalar double precision floating-point value from xmm2 and xmm3 to xmm1 register. |
| VEX.LIG.F2.0F.WIG 10 /r | VMOVSD xmm1, m64 | D | V/V | AVX | Load scalar double precision floating-point value from m64 to xmm1 register. |
| VEX.LIG.F2.0F.WIG 11 /r | VMOVSD xmm1, xmm2, xmm3 | E | V/V | AVX | Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1. |
| VEX.LIG.F2.0F.WIG 11 /r | VMOVSD m64, xmm1 | C | V/V | AVX | Store scalar double precision floating-point value from xmm1 register to m64. |
| EVEX.LLIG.F2.0F.W1 10 /r | VMOVSD xmm1 {k1}{z}, xmm2, xmm3 | B | V/V | AVX512F OR AVX10.1 | Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1. |
| EVEX.LLIG.F2.0F.W1 10 /r | VMOVSD xmm1 {k1}{z}, m64 | V/V | F AVX512F OR AVX10.1 | Load scalar double precision floating-point value from m64 to xmm1 register under writemask k1. | |
| EVEX.LLIG.F2.0F.W1 11 /r | VMOVSD xmm1 {k1}{z}, xmm2, xmm3 | E | V/V | AVX512F OR AVX10.1 | Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1. |
| EVEX.LLIG.F2.0F.W1 11 /r | VMOVSD m64 {k1}, xmm1 | V/V | G AVX512F OR AVX10.1 | Store scalar double precision floating-point value from xmm1 register to m64 under writemask k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (r, w) | ModRM:r/m (r) | N/A | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
| C | N/A | ModRM:r/m (w) | ModRM:reg (r) | N/A | N/A |
| D | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Description
Moves a scalar double precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. This instruction can be used to move a double precision floating-point value to and from the low quadword of an XMM register and a 64-bit memory location, or to move a double precision floating-point value between the low quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations. Legacy version: When the source and destination operands are XMM registers, bits MAXVL:64 of the destination operand remains unchanged. When the source operand is a memory location and destination operand is an XMM
VEX and EVEX encoded register-register syntax: Moves a scalar double precision floating-point value from the second source operand (the third operand) to the low quadword element of the destination operand (the first operand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed. VEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAXVL:64 of the destination operand is cleared to all 0s. EVEX encoded versions: The low quadword of the destination is updated according to the writemask. Note: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instruction will #UD.
Operation
VMOVSD (EVEX.LLIG.F2.0F 10 /r: VMOVSD xmm1, m64 With Support for 32 Registers) IF k1[0] or *no writemask* THEN DEST[63:0] := SRC[63:0] ELSE IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged* ELSE ; zeroing-masking THEN DEST[63:0] := 0 FI; FI; DEST[MAXVL-1:64] := 0 VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD m64, xmm1 With Support for 32 Registers) IF k1[0] or *no writemask* THEN DEST[63:0] := SRC[63:0] ELSE *DEST[63:0] remains unchanged* ; merging-masking FI; VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3) IF k1[0] or *no writemask* THEN DEST[63:0] := SRC2[63:0] ELSE IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged* ELSE ; zeroing-masking THEN DEST[63:0] := 0 FI; FI; DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0 MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, xmm2) DEST[63:0] := SRC[63:0] DEST[MAXVL-1:64] (Unmodified) VMOVSD (VEX.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3) DEST[63:0] := SRC2[63:0] DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0 VMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3) DEST[63:0] := SRC2[63:0] DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0 VMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, m64) DEST[63:0] := SRC[63:0] DEST[MAXVL-1:64] := 0 MOVSD/VMOVSD (128-bit Versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1) DEST[63:0] := SRC[63:0] MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, m64) DEST[63:0] := SRC[63:0] DEST[127:64] := 0 DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p); VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p); VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a); VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a); VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s); MOVSD __m128d _mm_load_sd (double *p) MOVSD void _mm_store_sd (double *p, __m128d a) MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)