v4fnmaddss
Fused Negative Multiply-Add Scalar Single (4-iterations)
4-way Negative FMA for Neural Nets (Scalar).
Pseudocode Operation
for i in 0 to 3:
temp ← -(xmm2[i] * m128[i])
xmm1[i] ← temp + xmm1[i]
update_MXCSR_flags(temp, xmm1[i])Example
Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
XMM register pair (consecutive even+odd registers) -
src2
128-bit memory operand
Related
More in AVX-512-4FMAPS
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.LLIG.F2.0F38.W0 9B /r | V4FMADDSS xmm1{k1}{z}, xmm2+3, m128 | A | V/V | AVX512_4FMAPS | Multiply scalar single precision floating-point values from source register block indicated by xmm2 by values from m128 and accumulate the result in xmm1. |
| EVEX.LLIG.F2.0F38.W0 AB /r | V4FNMADDSS xmm1{k1}{z}, xmm2+3, m128 | A | V/V | AVX512_4FMAPS | Multiply and negate scalar single precision floating-point values from source register block indicated by xmm2 by values from m128 and accumulate the result in xmm1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Tuple1_4X | ModRM:reg (r, w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
This instruction computes 4 sequential scalar fused single precision floating-point multiply-add instructions with a sequentially selected memory operand in each of the four steps. In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand. This instruction supports memory fault suppression. The entire memory operand is loaded if the least significant mask bit is set to 1 or if a “no masking” encoding is used. The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation portion of this instruction. Rounding is performed at every FMA boundary. Exceptions are also taken sequentially. Pre- and post-computational exceptions of the first FMA take priority over the pre- and post-computational exceptions of the second FMA, etc.
Operation
src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.
define NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg):
tmpdest := dest
// reg[] is an array representing the SIMD register file.
IF k1[0] or *no writemask*:
FOR j := 0 to regs_loaded - 1:
IF posneg = 0:
tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] - reg[src_base + j ].single[0] * msrc.single[j])
ELSE:
tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] + reg[src_base + j ].single[0] * msrc.single[j])
ELSE IF *zeroing*:
tmpdest.single[0] := 0
dest := tmpdst
dest[MAX_VL-1:VL] := 0
V4FMADDSS and V4FNMADDSS dest{k1}, src1, msrc (AVX512)
VL = 128
regs_loaded := 4
src_base := src_reg_id & ~3 // for src1 operand
posneg := 0 if negative form, 1 otherwise
NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg)Intel C/C++ Compiler Intrinsic Equivalent
V4FMADDSS __m128 _mm_4fmadd_ss(__m128, __m128x4, __m128 *); V4FMADDSS __m128 _mm_mask_4fmadd_ss(__m128, __mmask8, __m128x4, __m128 *); V4FMADDSS __m128 _mm_maskz_4fmadd_ss(__mmask8, __m128, __m128x4, __m128 *); V4FNMADDSS __m128 _mm_4fnmadd_ss(__m128, __m128x4, __m128 *); V4FNMADDSS __m128 _mm_mask_4fnmadd_ss(__m128, __mmask8, __m128x4, __m128 *); V4FNMADDSS __m128 _mm_maskz_4fnmadd_ss(__mmask8, __m128, __m128x4, __m128 *);