andps

Bitwise Logical AND Packed Single-Precision

ANDPS xmm, xmm/m128

Bitwise AND of 128 bits.

Details

The Bitwise Logical AND Packed Single-Precision instruction bitwise AND of 128 bits.

Pseudocode Operation

DEST <- DEST AND SRC
// Flags affected: SF, ZF, PF (OF=CF=0)

Example

ANDPS xmm0, xmm1

Encoding

Binary Layout
0F
+0
54
+1
 
Format SSE
Opcode 0F 54
Extension SSE

Operands

  • dest
    128-bit SSE/AVX register (XMM)
  • src
    128-bit XMM register or 128-bit memory