movzx

Move with Zero-Extension

MOVZX r, r/m

Copies and zero-extends a smaller value to a larger register.

Details

Moves a value from a smaller source operand (8 or 16 bits) to a larger destination register, zero-extending the value to fill the destination width. All high-order bits of the destination beyond the source width are cleared to zero. No flags are affected by this instruction. Supported size combinations: r16 ← r/m8, r32 ← r/m8, r32 ← r/m16, r64 ← r/m8, r64 ← r/m16.

Pseudocode Operation

dest ← (source_width < dest_width) ? (zero_extend(src, dest_width)) : src;

Example

MOVZX rax, rbx

Encoding

Binary Layout
0F
+0
B6
+1
 
Format Legacy
Opcode 0F B6
Extension Base

Operands

  • dest
    General-purpose register
  • src
    Register or memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
0F B6 /r MOVZX r16, r/m8 RM Valid Valid Move byte to word with zero-extension.
0F B6 /r MOVZX r32, r/m8 RM Valid Valid Move byte to doubleword, zero-extension.
REX.W + 0F B6 /r MOVZX r64, r/m8 RM Valid N.E. Move byte to quadword, zero-extension.
0F B7 /r MOVZX r32, r/m16 RM Valid Valid Move word to doubleword, zero-extension.
REX.W + 0F B7 /r MOVZX r64, r/m16 RM Valid N.E. Move word to quadword, zero-extension.

Description

Copies the contents of the source operand (register or memory location) to the destination operand (register) and zero extends the value. The size of the converted value depends on the operand-size attribute. In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := ZeroExtend(SRC);

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used. MOVZX—Move With Zero-Extend Vol. 2B 4-131

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. MOVZX—Move With Zero-Extend Vol. 2B 4-132