adc

Add with Carry

ADC r/m, r

Adds operands and the Carry Flag (CF).

Pseudocode Operation

result ← dest + src + CF
dest ← result
CF ← unsigned_overflow(dest_old, src, CF)
OF ← signed_overflow(dest_old, src, result)
ZF ← (result == 0)
SF ← (result_sign_bit == 1)
AF ← ((dest_old & 0xF) + (src & 0xF) + CF) > 0xF
PF ← popcount(result & 0xFF) is even

Example

ADC rbx, rax

Encoding

Binary Layout

Format Legacy

Opcode 11

Extension Base

Operands

dest
Reg/Mem
src
Reg

Across architectures

Add With Carry : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
14 ib	ADC AL, imm8	I	Valid Valid	Add with carry imm8 to AL.
15 iw	ADC AX, imm16	I	Valid Valid	Add with carry imm16 to AX.
15 id	ADC EAX, imm32	I	Valid Valid	Add with carry imm32 to EAX.
REX.W + 15 id	ADC RAX, imm32	I	Valid N.E.	Add with carry imm32 sign extended to 64bits to RAX.
80 /2 ib	ADC r/m8, imm8	MI	Valid Valid	Add with carry imm8 to r/m8.
81 /2 iw	ADC r/m16, imm16	MI	Valid Valid	Add with carry imm16 to r/m16.
81 /2 id	ADC r/m32, imm32	MI	Valid Valid	Add with CF imm32 to r/m32.
REX.W + 81 /2 id	ADC r/m64, imm32	MI	Valid N.E.	Add with CF imm32 sign extended to 64-bits to r/m64.
83 /2 ib	ADC r/m16, imm8	MI	Valid Valid	Add with CF sign-extended imm8 to r/m16.
83 /2 ib	ADC r/m32, imm8	MI	Valid Valid	Add with CF sign-extended imm8 into r/m32.
REX.W + 83 /2 ib	ADC r/m64, imm8	MI	Valid N.E.	Add with CF sign-extended imm8 into r/m64.
10 /r	ADC r/m8, r8	MR	Valid Valid	Add with carry byte register to r/m8.
11 /r	ADC r/m16, r16	MR	Valid Valid	Add with carry r16 to r/m16.
11 /r	ADC r/m32, r32	MR	Valid Valid	Add with CF r32 to r/m32.
REX.W + 11 /r	ADC r/m64, r64	MR	Valid N.E.	Add with CF r64 to r/m64.
12 /r	ADC r8, r/m8	RM	Valid Valid	Add with carry r/m8 to byte register.
13 /r	ADC r16, r/m16	RM	Valid Valid	Add with carry r/m16 to r16.
13 /r	ADC r32, r/m32	RM	Valid Valid	Add with CF r/m32 to r32.
REX.W + 13 /r	ADC r64, r/m64	RM	Valid N.E.	Add with CF r/m64 to r64.

Description

Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format. The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result. The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := DEST + SRC + CF;

Intel C/C++ Compiler Intrinsic Equivalent

ADC extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);
ADC extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short *sum_out);
ADC extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);
ADC extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64
*sum_out);

Flags Affected

The OF, SF, ZF, AF, CF, and PF flags are set according to the result.

Exceptions

Protected Mode Exceptions

#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ADC-Add With Carry Vol. 2A 3-10 #UD If the LOCK prefix is used but the destination is not a memory operand. ADC-Add With Carry Vol. 2A 3-11

adc