shrx

Shift Logical Right Without Affecting Flags

SHRX r32, r/m32, r32

Logical right shift, count in register. No flags update.

Details

Shift Logical Right Without Affecting Flags performs a logical right shift of the source operand by a count held in a register, storing the result in the destination, without modifying any arithmetic flags. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

Pseudocode Operation

count ← src2 & ((operand_size == 64) ? 0x3F : 0x1F); dest ← src1 >> count;

Example

SHRX eax, ebx, eax

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.F2.0F38.W0 F7 /r
Extension BMI2

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src1
    32-bit register or memory
  • src2
    32-bit general-purpose register (e.g. EAX)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.F3.0F38.W0 F7 /r SARX r32a, r/m32, r32b RMV V/V BMI2 Shift r/m32 arithmetically right with count specified in r32b and load into r32a.
VEX.LZ.66.0F38.W0 F7 /r SHLX r32a, r/m32, r32b RMV V/V BMI2 Shift r/m32 logically left with count specified in r32b and load into r32a.
VEX.LZ.F2.0F38.W0 F7 /r SHRX r32a, r/m32, r32b RMV V/V BMI2 Shift r/m32 logically right with count specified in r32b and load into r32a.
VEX.LZ.F3.0F38.W1 F7 /r SARX r64a, r/m64, r64b RMV V/N.E. BMI2 Shift r/m64 arithmetically right with count specified in r64b and load into r64a.
VEX.LZ.66.0F38.W1 F7 /r SHLX r64a, r/m64, r64b RMV V/N.E. BMI2 Shift r/m64 logically left with count specified in r64b and load into r64a.
VEX.LZ.F2.0F38.W1 F7 /r SHRX r64a, r/m64, r64b RMV V/N.E. BMI2 Shift r/m64 logically right with count specified in r64b and load into r64a.

Description

Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in the second source operand (the third operand). The result is written to the destination operand (the first operand). The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit) while shifting. The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit locations). This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD. If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked. SARX,SHRX, and SHLX instructions do not update flags.

Operation

TEMP := SRC1;
IF VEX.W1 and CS.L = 1
THEN
countMASK := 3FH;
ELSE
countMASK := 1FH;
FI
COUNT := SRC2 AND countMASK;

DO WHILE (COUNT ≠ 0)
IF instruction is SHLX
THEN
TEMP := TEMP *2;



SARX/SHLX/SHRX—Shift Without Affecting Flags                                                                                               Vol. 2B 4-608
ELSE IF instruction is SHRX
THEN
TEMP := TEMP /2; //unsigned divide
ELSE           // SARX
TEMP := TEMP /2; // signed divide, round toward negative infinity
FI;
COUNT := COUNT - 1;
OD
DEST := TEMP;

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” SARX/SHLX/SHRX—Shift Without Affecting Flags Vol. 2B 4-609