sha256msg2

SHA256 Message Schedule 2

SHA256MSG2 xmm1, xmm2/m128

Performs final calculation for SHA256 message schedule.

Details

Performs the final calculation of the SHA256 message schedule for the next 4 message words. The instruction operates on 128-bit XMM registers containing 32-bit message schedule values and combines them with the previous message schedule state. All flags (CF, PF, AF, ZF, SF, OF) remain unchanged; this is a pure data-transformation instruction with no flag effects.

Pseudocode Operation

xmm1[127:0] ← SHA256_MSG_SCHEDULE_ROUND(xmm1[127:0], xmm2/m128[127:0])

Example

SHA256MSG2 xmm1, xmm2/m128

Encoding

Binary Layout
0F
+0
38
+1
CD
+2
 
Format Legacy
Opcode NP 0F 38 CD /r
Extension SHA

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
NP 0F 38 CD /r SHA256MSG2 xmm1, xmm2/m128 RM V/V SHA Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.

Description

The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the final calculation for the next four SHA256 message dwords.

Operation

SHA256MSG2
W14 := SRC2[95:64] ;
W15 := SRC2[127:96] ;
W16 := SRC1[31: 0] + σ1( W14) ;
W17 := SRC1[63: 32] + σ1( W15) ;
W18 := SRC1[95: 64] + σ1( W16) ;
W19 := SRC1[127: 96] + σ1( W17) ;

DEST[127:96] := W19 ;
DEST[95:64] := W18 ;
DEST[63:32] := W17 ;
DEST[31:0] := W16;

Intel C/C++ Compiler Intrinsic Equivalent

SHA256MSG2 __m128i _mm_sha256msg2_epu32(__m128i, __m128i);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.” SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords Vol. 2B 4-636