vpternlogq

Packed Quadword Ternary Logic

VPTERNLOGQ zmm1 {k1}, zmm2, zmm3/m512, imm8

Performs one of 256 logical operations on 3 quadwords.

Details

The Packed Quadword Ternary Logic instruction performs one of 256 logical operations on 3 quadwords.

Pseudocode Operation

// Performs one of 256 logical operations on 3 quadwords

Example

VPTERNLOGQ zmm1, zmm2, zmm3/m512, 3

Encoding

Binary Layout
EVEX
+0
66
+4
0F
+5
3A
+6
25
+7
 
Format EVEX
Opcode 66 0F 3A 25
Extension AVX-512F

Operands

  • dest
    512-bit ZMM AVX-512 register
  • src1
    512-bit ZMM AVX-512 register
  • src2
    512-bit ZMM AVX-512 register or Memory operand
  • src3
    8-bit signed immediate