movntss

Move Non-Temporal Scalar Single

MOVNTSS m32, xmm1

Stores scalar float bypassing cache (AMD SSE4a).

Pseudocode Operation

[dest] ← src[31:0];

Example

MOVNTSS [rbp-4], xmm1

Encoding

Binary Layout

F3

+0

0F

+1

2B

+2

 

Format SSE4a

Opcode F3 0F 2B /r

Extension SSE4a

Operands

• dest
  32-bit memory operand
• src
  128-bit XMM SIMD register

Related

More in SSE4a

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ AMD APM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
F3 0F 2B /r	MOVNTSS m32, xmm1				Non-temporal store of the low scalar single-precision value in xmm1 to m32.

Description

Single-Precision Floating-Point Stores one single-precision floating-point value from an XMM register to a 32-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining memory write, which minimizes cache pollution. The diagram below illustrates the operation of this instruction: mem32 XMM register

31 0 127 31 0 copy

Flags Affected

None 220 [AMDMOVNTSSPublic Use] Instruction Reference