movntss

Move Non-Temporal Scalar Single

MOVNTSS m32, xmm1

Stores scalar float bypassing cache (AMD SSE4a).

Details

Stores the low 32-bit scalar single-precision floating-point value from an XMM register to a 32-bit memory location, bypassing the cache hierarchy using non-temporal semantics. The instruction issues a weakly-ordered write that avoids polluting the L1/L2 caches, useful for streaming writes. No arithmetic flags are affected; this is a memory store only.

Pseudocode Operation

[dest] ← src[31:0];

Example

MOVNTSS [rbp-4], xmm1

Encoding

Binary Layout
F3
+0
0F
+1
2B
+2
 
Format SSE4a
Opcode F3 0F 2B /r
Extension SSE4a

Operands

  • dest
    32-bit memory operand
  • src
    128-bit XMM SIMD register

Reference (AMD APM)

Description

Single-Precision Floating-Point Stores one single-precision floating-point value from an XMM register to a 32-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining memory write, which minimizes cache pollution. The diagram below illustrates the operation of this instruction: mem32 XMM register 31 0 127 31 0 copy

Flags Affected

None 220 [AMDMOVNTSSPublic Use] Instruction Reference