vpclmulqdq

Vector Carry-Less Multiplication (AVX512)

VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8

Carry-less multiply on 512-bit vector.

Details

Performs carry-less multiplication of 64-bit elements from two 512-bit vectors, producing 128-bit results that are stored in the destination ZMM register. The imm8 field selects which 64-bit quadwords from the source operands participate in the multiplication. No flags are affected; this is a cryptographic primitive used in GCM and other authenticated encryption modes.

Pseudocode Operation

for i in 0 to 3:
  qw1 = (imm8[0] == 0) ? zmm2[i*64..i*64+63] : zmm2[i*64+64..i*64+127]
  qw2 = (imm8[4] == 0) ? zmm3[i*64..i*64+63] : zmm3[i*64+64..i*64+127]
  zmm1[i*128..i*128+127] ← carryless_multiply(qw1, qw2)

Example

VPCLMULQDQ zmm1, zmm2, zmm3/m512, 3

Encoding

Binary Layout

EVEX

Format EVEX

Opcode VEX.128.66.0F3A.WIG 44 /r ib

Extension AVX-512-VPCLMULQDQ

Operands

dest
512-bit ZMM AVX-512 register
src1
512-bit ZMM AVX-512 register
src2
512-bit ZMM AVX-512 register or Memory operand
src3
8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
66 0F 3A 44 /r ib	PCLMULQDQ	A	V/V		Performs carry-less multiplication of one PCLMULQDQ xmm1, xmm2/m128, imm8 quadword of xmm1 by one quadword of xmm2/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm1 and xmm2/m128 should be used.
VEX.128.66.0F3A.WIG 44 /r ib	PCLMULQDQ	B	V/V	AVX	Performs carry-less multiplication of one VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8 quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.
VEX.256.66.0F3A.WIG 44 /r /ib	VPCLMULQDQ	B	V/V	AVX	For each 128-bit lane, performs two carry-less VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8 multiplications of one quadword of ymm2 by one quadword of ymm3/m256, stores the two 128-bit results in ymm1. The immediate is used to determine which quadword in each 128-bit lane of ymm2 and ymm3/m256 should be used.
EVEX.128.66.0F3A.WIG 44 /r /ib	VPCLMULQDQ	C	V/V	(AVX512VL OR AVX10.1)	Performs carry-less multiplication of one VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8 quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The immediate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.
EVEX.256.66.0F3A.WIG 44 /r /ib	VPCLMULQDQ	C	V/V	(AVX512VL OR AVX10.1)	For each 128-bit lane, performs two carry-less VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8 multiplications of one quadword of ymm2 by one quadword of ymm3/m256, stores the two 128-bit results in ymm1. The immediate is used to determine which quadword in each 128-bit lane of ymm2 and ymm3/m256 should be used.
EVEX.512.66.0F3A.WIG 44 /r /ib	VPCLMULQDQ	C	V/V	(AVX512F OR AVX10.1)	For each 128-bit lane, performs two carry-less VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8 multiplications of one quadword of zmm2 by one quadword of zmm3/m512, stores the four 128-bit results in zmm1. The immediate is used to determine which quadword in each 128-bit lane of zmm2 and zmm3/m512 should be used.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (r, w)	ModRM:r/m (r)	imm8	N/A
B	N/A	ModRM:reg (w)	VEX.vvvv (r)	ModRM:r/m (r)	imm8
C	Full Mem	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	imm8 (r)

Description

Performs packed carry-less multiplication of quadword pairs. XMM versions perform a single multiply of a pair of PCLMULQDQ—Carry-Less Multiplication Quadword Vol. 2B 4-242 quadwords. YMM versions perform two packed multiplies of pairs of quadwords. ZMM versions perform four packed multiplies of pairs of quadwords. Bits 4 and 0 are used to select which 64-bit half of each operand to use according to Table 4-14, other bits of the immediate byte are ignored. The EVEX encoded form of this instruction does not support memory fault suppression. Table 4-14. PCLMULQDQ Quadword Selection of Immediate Byte Imm[4] Imm[0] PCLMULQDQ Operation 0 0 CL_MUL( SRC21[63:0], SRC1[63:0] ) 0 1 CL_MUL( SRC2[63:0], SRC1[127:64] ) 1 0 CL_MUL( SRC2[127:64], SRC1[63:0] ) 1 1 CL_MUL( SRC2[127:64], SRC1[127:64] )

Operation

define PCLMUL128(X,Y):                     // helper function
FOR i := 0 to 63:
TMP [ i ] := X[ 0 ] and Y[ i ]
FOR j := 1 to i:
TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])
DEST[ i ] := TMP[ i ]
FOR i := 64 to 126:
TMP [ i ] := 0
FOR j := i - 63 to 63:
TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])
DEST[ i ] := TMP[ i ]
DEST[127] := 0;
RETURN DEST                            // 128b vector





PCLMULQDQ—Carry-Less Multiplication Quadword                                                                                              Vol. 2B 4-243
PCLMULQDQ (SSE Version)
IF imm8[0] = 0:
TEMP1 := SRC1.qword[0]
ELSE:
TEMP1 := SRC1.qword[1]
IF imm8[4] = 0:
TEMP2 := SRC2.qword[0]
ELSE:
TEMP2 := SRC2.qword[1]
DEST[127:0] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:128] (Unmodified)

VPCLMULQDQ (128b and 256b VEX Encoded Versions)
(KL,VL) = (1,128), (2,256)
FOR i= 0 to KL-1:
IF imm8[0] = 0:
TEMP1 := SRC1.xmm[i].qword[0]
ELSE:
TEMP1 := SRC1.xmm[i].qword[1]
IF imm8[4] = 0:
TEMP2 := SRC2.xmm[i].qword[0]
ELSE:
TEMP2 := SRC2.xmm[i].qword[1]
DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:VL] := 0

VPCLMULQDQ (EVEX Encoded Version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i = 0 to KL-1:
IF imm8[0] = 0:
TEMP1 := SRC1.xmm[i].qword[0]
ELSE:
TEMP1 := SRC1.xmm[i].qword[1]
IF imm8[4] = 0:
TEMP2 := SRC2.xmm[i].qword[0]
ELSE:
TEMP2 := SRC2.xmm[i].qword[1]
DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)
DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

(V)PCLMULQDQ __m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)
VPCLMULQDQ __m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);
VPCLMULQDQ __m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions,” additionally: #UD If VEX.L = 1. EVEX-encoded: See Table 2-52, “Type E4NF Class Exception Conditions.” PCLMULQDQ—Carry-Less Multiplication Quadword Vol. 2B 4-244