vpshaq
Vector Packed Shift Arithmetic Quadword
VPSHAQ xmm1, xmm2/m128, xmm3
Shifts quadwords arithmetically.
Details
Shifts each 64-bit quadword in xmm2/m128 arithmetically by the signed immediate count, storing results in xmm1. Arithmetic right shifts maintain the sign bit; left shifts fill with zeros. This XOP extension instruction operates on 128-bit packed quadword data and does not affect EFLAGS.
Pseudocode Operation
for i = 0 to 1 {
if (imm8 >= 0) {
xmm1[64*i:64*i+63] ← (xmm2/m128[64*i:64*i+63]) << imm8
} else {
xmm1[64*i:64*i+63] ← (xmm2/m128[64*i:64*i+63]) >> (-imm8) // arithmetic shift
}
}Example
VPSHAQ xmm1, xmm2/m128, 3
Encoding
Binary Layout
VEX
+0
opcode
+3
ModRM
+4
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.count.0.00 9B /r | VPSHAQ xmm1, xmm2/mem128, xmm3 | ||||
| 8F RXB.09 1.src.0.00 9B /r | VPSHAQ xmm1, xmm2, xmm3/mem128 |
Description
Quadwords
Shifts each signed quadword of the source as specified by a count byte and writes the result to the corresponding quadword of the destination.
The count bytes are 8-bit signed two's-complement values located in the low-order byte of the corresponding quadword element of the count operand.
When the count value is positive, bits are shifted to the left (toward the more significant bit positions).
Zeros are shifted in at the right end (least-significant bit) of the quadword.
When the count value is negative, bits are shifted to the right (toward the least significant bit positions). The most significant bit is replicated and shifted in at the left end (most-significant bit) of the quadword.
The shift amount is stored in two’s-complement form. The count is modulo 64.
There are three operands: VPSHAQ dest, src, count
The destination (dest) is an XMM register specified by ModRM.reg.
Both src and count are configured by XOP.W.
• When XOP.W = 0, count is an XMM register specified by XOP.vvvv and src is either an XMM register or a memory location specified by ModRM.r/m.
• When XOP.W = 1, count is either an XMM register or a memory location specified by
ModRM.r/m and src is an XMM register specified by XOP.vvvv.
Bits [255:128] of the YMM register that corresponds to the destination are cleared.
Exceptions
Exceptions
Mode
Exception Cause of Exception
Real Virt Prot
X Instruction not supported, as indicated by CPUID feature identifier.
X X XOP instructions are only recognized in protected mode.
X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE].
Invalid opcode, #UD X XFEATURE_ENABLED_MASK[2:1] ! = 11b.
X XOP.L = 1.
X REX, F2, F3, or 66 prefix preceding XOP prefix.
X Lock prefix (F0h) preceding opcode.
Device not available, #NM X CR0.TS = 1.
Stack, #SS X Memory address exceeding stack segment limit or non-canonical.
X Memory address exceeding data segment limit or non-canonical.
General protection, #GP
X Null data segment used to reference memory.
Page fault, #PF X Instruction execution caused a page fault.
Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled.
X — XOP exception
834 [AMD VPSHAQPublic Use] Instruction Reference