vpshaq

Vector Packed Shift Arithmetic Quadword

VPSHAQ xmm1, xmm2/m128, imm8

Shifts quadwords arithmetically.

Details

The Vector Packed Shift Arithmetic Quadword instruction shifts quadwords arithmetically.

Pseudocode Operation

// Shifts quadwords arithmetically

Example

VPSHAQ xmm1, xmm2/m128, 3

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format XOP
Opcode 8F ... 9B
Extension XOP

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register or Memory operand
  • src2
    8-bit signed immediate