pdep

Parallel Bits Deposit

PDEP r32, r32, r/m32

Scatters bits from LSB of source to positions marked in mask.

Details

Parallel Bits Deposit scatters bits from the LSB of the first source operand to positions marked by set bits in the mask operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; operand size can be 32 or 64 bits.

Pseudocode Operation

result ← 0; src_bit ← 0; for (i = 0; i < operand_size; i++) { if (src2[i]) { result[i] ← src1[src_bit]; src_bit += 1; } } dest ← result;

Example

PDEP eax, eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.F2.0F38.W0 F5 /r
Extension BMI2

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src1
    32-bit general-purpose register (e.g. EAX)
  • src2
    32-bit register or memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.F2.0F38.W0 F5 /r PDEP r32a, r32b, r/m32 RVM V/V BMI2 Parallel deposit of bits from r32b using mask in r/m32, result is written to r32a.
VEX.LZ.F2.0F38.W1 F5 /r PDEP r64a, r64b, r/m64 RVM V/N.E. BMI2 Parallel deposit of bits from r64b using mask in r/m64, result is written to r64a.

Description

PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits from the first source operand and deposit them in the destination operand at the corresponding bit locations that are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero. SRC1 S31 S30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0 SRC2 0 0 0 1 0 1 0 1 0 0 1 0 0 (mask) DEST 0 0 0 S3 0 S2 0 S1 0 0 S0 0 0 bit 31 bit 0 Figure 4-8. PDEP Example This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

TEMP := SRC1;
MASK := SRC2;
DEST := 0 ;
m := 0, k := 0;
DO WHILE m < OperandSize

IF MASK[ m] = 1 THEN
DEST[ m] := TEMP[ k];
k := k+ 1;
FI
m := m+ 1;
OD


PDEP—Parallel Bits Deposit                                                                                                                       Vol. 2B 4-282

Intel C/C++ Compiler Intrinsic Equivalent

PDEP unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);
PDEP unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” PDEP—Parallel Bits Deposit Vol. 2B 4-283