aeskeygenassist
AES Key Generation Assist
Generates round key for AES encryption.
Pseudocode Operation
dest[127:0] ← AES_KeyGenAssist(src[127:0], imm8);
OF ← 0; CF ← 0; ZF ← 0; SF ← 0; AF ← 0; PF ← 0;Example
Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Related
More in AES-NI
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F 3A DF /r ib | AESKEYGENASSIST xmm1, xmm2/m128, imm8 | RMI | V/V | AES | Assist in AES round key generation using an 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1. |
| VEX.128.66.0F3A.WIG DF /r ib | VAESKEYGENASSIST xmm1, xmm2/m128, imm8 | RMI | V/V | Both AES Assist in AES round key generation using 8 and bits Round Constant (RCON) specified in the AVX flags immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1. |
Description
Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using 128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the result in the destination operand. The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location. 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESKEYGENASSIST X3[31:0] := SRC [127: 96]; X2[31:0] := SRC [95: 64]; X1[31:0] := SRC [63: 32]; X0[31:0] := SRC [31: 0]; RCON[31:0] := ZeroExtend(imm8[7:0]); DEST[31:0] := SubWord(X1); DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON; DEST[95:64] := SubWord(X3); DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON; DEST[MAXVL-1:128] (Unmodified) VAESKEYGENASSIST X3[31:0] := SRC [127: 96]; X2[31:0] := SRC [95: 64]; X1[31:0] := SRC [63: 32]; X0[31:0] := SRC [31: 0]; RCON[31:0] := ZeroExtend(imm8[7:0]); DEST[31:0] := SubWord(X1); DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON; DEST[95:64] := SubWord(X3); DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON; DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESKEYGENASSIST __m128i _mm_aeskeygenassist (__m128i, const int)