clzero

Zero Cache Line

CLZERO

Clears the cache line at address RAX/EAX (AMD).

Pseudocode Operation

lineaddr ← RAX & ~0x3F; memset([lineaddr], 0, 64);

Encoding

Binary Layout

0F

+0

01

+1

FC

+2

 

Format AMD

Opcode 0F 01 FC

Extension CLZERO

Operands

Related

More in CLZERO

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ AMD APM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
0F 01 FC	CLZERO rAX				Clears cache line containing rAX

Description

Clears the cache line specified by the logical address in rAX by writing a zero to every byte in the line. The instruction uses an implied non temporal memory type, similar to a streaming store, and uses the write combining protocol to minimize cache pollution. CLZERO is weakly-ordered with respect to other instructions that operate on memory. Software should use an SFENCE or stronger to enforce memory ordering of CLZERO with respect to other store instructions. The CLZERO instruction executes at any privilege level. CLZERO performs all the segmentation and paging checks that a store of the specified cache line would perform. The CLZERO instruction is supported if the feature flag CPUID Fn8000_0008_EBX[CLZERO] is set. The 8-bit field CPUID Fn 0000_0001_EBX[CLFlush] returns the size of the cacheline in quadwords.

Flags Affected

None

Exceptions

Exceptions

Virtual Exception (vector) Real 8086 Protected Cause of Exception Instruction not supported by CPUID Invalid opcode, #UD X X X Fn8000_0008_EBX[CLZERO] = 0 A memory address exceeded the stack segment limit Stack, #SS X X X or was non-canonical. A memory address exceeded a data segment limit or General protection, X X X was non-canonical. #GP X A null data segment was used to reference memory. A page fault resulted from the execution of the Page fault, #PF X X instruction. 150 General-Purpose