ptest
Packed Logical Comparison
Bitwise compare of 128-bit value (AND) setting flags.
Pseudocode Operation
temp ← dest[127:0] AND src[127:0];
ZF ← (temp == 0);
CF ← ((src[127:0] AND (NOT dest[127:0])) == 0);
OF ← 0; SF ← 0; AF ← 0; PF ← 0;Encoding
Operands
-
dest
128-bit XMM SIMD register -
src
128-bit XMM SIMD register or Memory operand
Related
More in SSE4.1
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F 38 17 /r | PTEST xmm1, xmm2/m128 | RM | V/V | SSE4_1 | Set ZF if xmm2/m128 AND xmm1 result is all 0s. Set CF if xmm2/m128 AND NOT xmm1 result is all 0s. |
| VEX.128.66.0F38.WIG 17 /r | VPTEST xmm1, xmm2/m128 | RM | V/V | AVX | Set ZF and CF depending on bitwise AND and ANDN of sources. |
| VEX.256.66.0F38.WIG 17 /r | VPTEST ymm1, ymm2/m256 | RM | V/V | AVX | Set ZF and CF depending on bitwise AND and ANDN of sources. |
Description
PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first operand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of the bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand. The first source register is specified by the ModR/M reg field. 128-bit versions: The first source register is an XMM register. The second source register can be an XMM register or a 128-bit memory location. The destination register is not modified. VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM register or a 256-bit memory location. The destination register is not modified. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
(V)PTEST (128-bit Version) IF (SRC[127:0] BITWISE AND DEST[127:0] = 0) THEN ZF := 1; ELSE ZF := 0; IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0) THEN CF := 1; ELSE CF := 0; DEST (unmodified) AF := OF := PF := SF := 0; VPTEST (VEX.256 Encoded Version) IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF := 1; ELSE ZF := 0; IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF := 1; ELSE CF := 0; DEST (unmodified) AF := OF := PF := SF := 0;
Intel C/C++ Compiler Intrinsic Equivalent
PTEST int _mm_testz_si128 (__m128i s1, __m128i s2); PTEST int _mm_testc_si128 (__m128i s1, __m128i s2); PTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2); VPTEST int _mm256_testz_si256 (__m256i s1, __m256i s2); VPTEST int _mm256_testc_si256 (__m256i s1, __m256i s2); VPTEST int _mm256_testnzc_si256 (__m256i s1, __m256i s2); VPTEST int _mm_testz_si128 (__m128i s1, __m128i s2); VPTEST int _mm_testc_si128 (__m128i s1, __m128i s2); VPTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2);