vpcmov
Vector Packed Conditional Move
Bitwise conditional move based on selector.
Pseudocode Operation
for i in 0 to 127:
if (xmm4[i] == 1):
xmm1[i] ← xmm3[i]
else:
xmm1[i] ← xmm2[i]Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register -
src2
128-bit XMM SIMD register -
src3
128-bit XMM SIMD register
Related
More in XOP
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.08 0.src1.0.00 A2 /r ib | VPCMOV xmm1, xmm2, xmm3/mem128, xmm4 | ||||
| 8F RXB.08 0.src1.1.00 A2 /r ib | VPCMOV ymm1, ymm2, ymm3/mem256, ymm4 | ||||
| 8F RXB.08 1.src1.0.00 A2 /r ib | VPCMOV xmm1, xmm2, xmm3, xmm4/mem128 | ||||
| 8F RXB.08 1.src1.1.00 A2 /r ib | VPCMOV ymm1, ymm2, ymm3, ymm4/mem256 |
Description
Moves bits of either the first source or the second source to the corresponding positions in the destination, depending on the value of the corresponding bit of a third source. When a bit of the third source = 1, the corresponding bit of the first source is moved to the destination; when a bit of the third source = 0, the corresponding bit of the second source is moved to the destination. This instruction directly implements the C-language ternary “?” operation on each source bit. Arbitrary bit-granular predicates can be constructed by any number of methods, or loaded as constants from memory. This instruction may use the results of any SSE instructions as the predicate in the selector. VPCMPEQB (VPCMPGTB), VPCMPEQW (VPCMPGTW), VPCMPEQD (VPCMPGTD) and VPCMPEQQ (VPCMPGTQ) compare bytes, words, doublewords, quadwords and integers, respectively, and set the predicate in the destination to masks of 1s and 0s accordingly. VCMPPS (VCMPSS) and VCMPPD (VCMPSD) compare word and doubleword floating-point source values, respectively, and provide the predicate for the floating-point instructions. There are four operands: VPCMOV dest, src1, src2, src3. The first source (src1) is an XMM or YMM register specified by XOP.vvvv. XOP.W and bits [7:4] of an immediate byte (imm8) configure src2 and src3: • When XOP.W = 0, src2 is either a register or a memory location specified by ModRM.r/m and src3 is a register specified by imm8[7:4]. • When XOP.W = 1, src2 is a register specified by imm8[7:4] and src3 is either a register or a memory location specified by ModRM.r/m. The destination (dest) is either an XMM or a YMM register, as determined by XOP.L. When the destination is an XMM register, bits [255:128] of the corresponding YMM register are cleared.