vpcmov
Vector Packed Conditional Move
VPCMOV xmm1, xmm2, xmm3, xmm4
Bitwise conditional move based on selector.
Details
Performs bitwise conditional move on packed 128-bit XMM data using a selector register. For each bit in the selector (xmm4), if the bit is set (1), the corresponding bit from xmm3 is selected; otherwise, the bit from xmm2 is selected. Result is stored in xmm1. No flags are modified.
Pseudocode Operation
for i in 0 to 127:
if (xmm4[i] == 1):
xmm1[i] ← xmm3[i]
else:
xmm1[i] ← xmm2[i]Example
VPCMOV xmm1, xmm2, xmm3, xmm4
Encoding
Binary Layout
08
+0
A2
+1
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register -
src2
128-bit XMM SIMD register -
src3
128-bit XMM SIMD register
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.08 0.src1.0.00 A2 /r ib | VPCMOV xmm1, xmm2, xmm3/mem128, xmm4 | ||||
| 8F RXB.08 0.src1.1.00 A2 /r ib | VPCMOV ymm1, ymm2, ymm3/mem256, ymm4 | ||||
| 8F RXB.08 1.src1.0.00 A2 /r ib | VPCMOV xmm1, xmm2, xmm3, xmm4/mem128 | ||||
| 8F RXB.08 1.src1.1.00 A2 /r ib | VPCMOV ymm1, ymm2, ymm3, ymm4/mem256 |
Description
Moves bits of either the first source or the second source to the corresponding positions in the destination, depending on the value of the corresponding bit of a third source.
When a bit of the third source = 1, the corresponding bit of the first source is moved to the destination; when a bit of the third source = 0, the corresponding bit of the second source is moved to the destination.
This instruction directly implements the C-language ternary “?” operation on each source bit.
Arbitrary bit-granular predicates can be constructed by any number of methods, or loaded as constants from memory. This instruction may use the results of any SSE instructions as the predicate in the selector. VPCMPEQB (VPCMPGTB), VPCMPEQW (VPCMPGTW), VPCMPEQD (VPCMPGTD) and VPCMPEQQ (VPCMPGTQ) compare bytes, words, doublewords, quadwords and integers, respectively, and set the predicate in the destination to masks of 1s and 0s accordingly.
VCMPPS (VCMPSS) and VCMPPD (VCMPSD) compare word and doubleword floating-point source values, respectively, and provide the predicate for the floating-point instructions.
There are four operands: VPCMOV dest, src1, src2, src3.
The first source (src1) is an XMM or YMM register specified by XOP.vvvv.
XOP.W and bits [7:4] of an immediate byte (imm8) configure src2 and src3:
• When XOP.W = 0, src2 is either a register or a memory location specified by ModRM.r/m and src3 is a register specified by imm8[7:4].
• When XOP.W = 1, src2 is a register specified by imm8[7:4] and src3 is either a register or a memory location specified by ModRM.r/m.
The destination (dest) is either an XMM or a YMM register, as determined by XOP.L. When the destination is an XMM register, bits [255:128] of the corresponding YMM register are cleared.
Flags Affected
None None
Exceptions
Exceptions
Mode
Exception Cause of Exception
Real Virt Prot
X Instruction not supported, as indicated by CPUID feature identifier.
X X XOP instructions are only recognized in protected mode.
X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE].
Invalid opcode, #UD
X XFEATURE_ENABLED_MASK[2:1] ! = 11b.
X REX, F2, F3, or 66 prefix preceding XOP prefix.
X Lock prefix (F0h) preceding opcode.
Device not available, #NM X CR0.TS = 1.
Stack, #SS X Memory address exceeding stack segment limit or non-canonical.
X Memory address exceeding data segment limit or non-canonical.
General protection, #GP
X Null data segment used to reference memory.
Page fault, #PF X Instruction execution caused a page fault.
Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled.
X — XOP exception