vtestps

Packed Bit Test Single-Precision

VTESTPS xmm1, xmm2/m128

Sets ZF/CF based on sign bit comparisons of floats.

Details

The Packed Bit Test Single-Precision instruction sets ZF/CF based on sign bit comparisons of floats.

Pseudocode Operation

// Sets ZF/CF based on sign bit comparisons of floats

Example

VTESTPS xmm1, xmm2/m128

Encoding

Binary Layout
VEX
+0
66
+3
0F
+4
38
+5
0E
+6
 
Format AVX
Opcode 66 0F 38 0E
Extension AVX

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand