vpmovb2m

Move Byte Mask to Mask Register

VPMOVB2M k1, zmm1

Moves byte integer mask from ZMM to k-register.

Details

Extracts the most significant bit (MSB) from each byte element in a 512-bit ZMM register and compacts them into a 64-bit opmask register. The resulting mask register has one bit per original byte, forming a 64-bit result. Does not modify CPU flags; operates in 64-bit mode only with AVX-512BW.

Pseudocode Operation

mask_result = 0
for i = 0 to 63:
  if (src[8*i+7] != 0):
    mask_result |= (1 << i)
dest ← mask_result

Example

VPMOVB2M k1, zmm1

Encoding

Binary Layout

EVEX

opcode

ModRM

Format EVEX

Opcode EVEX.512.F3.0F38.W0 29 /r

Extension AVX-512BW

Operands

dest
AVX-512 opmask register (k0-k7)
src
512-bit ZMM AVX-512 register

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
EVEX.128.F3.0F38.W0 29 /r	VPMOVB2M k1, xmm1	RM	V/V	(AVX512VL AND AVX512BW) OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in XMM1.
EVEX.256.F3.0F38.W0 29 /r	VPMOVB2M k1, ymm1	RM	V/V	(AVX512VL AND AVX512BW) OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in YMM1.
EVEX.512.F3.0F38.W0 29 /r	VPMOVB2M k1, zmm1	RM	V/V	AVX512BW OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in ZMM1.
EVEX.128.F3.0F38.W1 29 /r	VPMOVW2M k1, xmm1	RM	V/V	(AVX512VL AND AVX512BW) OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in XMM1.
EVEX.256.F3.0F38.W1 29 /r	VPMOVW2M k1, ymm1	RM	V/V	(AVX512VL AND AVX512BW) OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in YMM1.
EVEX.512.F3.0F38.W1 29 /r	VPMOVW2M k1, zmm1	RM	V/V	AVX512BW OR AVX10.1	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in ZMM1.
EVEX.128.F3.0F38.W0 39 /r	VPMOVD2M k1, xmm1	RM	V/V	(AVX512VL AND AVX512DQ) OR AVX10.1 XMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in
EVEX.256.F3.0F38.W0 39 /r	VPMOVD2M k1, ymm1	RM	V/V	(AVX512VL AND AVX512DQ) OR AVX10.1 YMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in
EVEX.512.F3.0F38.W0 39 /r	VPMOVD2M k1, zmm1	RM	V/V	AVX512DQ OR AVX10.1 ZMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in
EVEX.128.F3.0F38.W1 39 /r	VPMOVQ2M k1, xmm1	RM	V/V	(AVX512VL AND AVX512DQ) OR AVX10.1 XMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in
EVEX.256.F3.0F38.W1 39 /r	VPMOVQ2M k1, ymm1	RM	V/V	(AVX512VL AND AVX512DQ) OR AVX10.1 YMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in
EVEX.512.F3.0F38.W1 39 /r	VPMOVQ2M k1, zmm1	RM	V/V	AVX512DQ OR AVX10.1 ZMM1.	Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in

Description

Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on the value of most significant bit of the corresponding element in the source register. The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask Vol. 2C 5-574

Operation

VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[i+7]
THEN    DEST[j] := 1
ELSE    DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[i+15]
THEN    DEST[j] := 1
ELSE    DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[i+31]
THEN    DEST[j] := 1
ELSE    DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0

VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[i+63]
THEN    DEST[j] := 1
ELSE    DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0





VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask                                                    Vol. 2C 5-575

Intel C/C++ Compiler Intrinsic Equivalent

VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-57, “Type E7NM Class Exception Conditions.” Additionally: #UD If EVEX.vvvv != 1111B. VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask Vol. 2C 5-576