vzeroupper

Zero Upper Bits of YMM Registers

VZEROUPPER

Clears bits 128-255 of all YMM registers (Avoids AVX-SSE transition penalty).

Details

Clears bits 128–255 of all 16 YMM registers (YMM0–YMM15 in 64-bit mode, YMM0–YMM7 in 32-bit mode), leaving bits 0–127 unchanged. This eliminates the AVX-to-SSE transition penalty by ensuring the upper 128-bit portions are zero before executing SSE instructions. No flags are affected. This instruction must be executed in protected or 64-bit mode.

Pseudocode Operation

for i from 0 to (is_64bit_mode ? 15 : 7) {
  YMM[i][128:255] ← 0;
}

Example

VZEROUPPER

Encoding

Binary Layout

VEX

Format VEX

Opcode VEX.128.0F.WIG 77

Extension AVX

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.128.0F.WIG 77	VZEROUPPER	ZO	V/V	AVX	Zero bits in positions 128 and higher of some YMM and ZMM registers.

Description

In 64-bit mode, the instruction zeroes the bits in positions 128 and higher in YMM0-YMM15 and ZMM0-ZMM15. Outside 64-bit mode, it zeroes those bits only in YMM0-YMM7 and ZMM0-ZMM7. VZEROUPPER does not modify the lower 128 bits of these registers and it does not modify ZMM16-ZMM31. This instruction is recommended when transitioning between AVX and legacy SSE code; it will eliminate performance penalties caused by false dependencies. Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm
registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,
ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits.

VZEROUPPER
IF (64-bit mode)
limit :=15
ELSE
limit := 7
FOR i in 0 .. limit:
simd_reg_file[i][MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROUPPER:     _mm256_zeroupper()

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.” VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers Vol. 2C 5-776 CHAPTER 6 6.1 INSTRUCTIONS (W-Z) Chapter 6 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (W-Z). See also: Chapter 3, “Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A; Chapter 4, “Instruction Set Reference, M-U‚” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B; and Chapter 5, “Instruction Set Reference, V‚” in the Intel® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 2D.