roundss
Round Scalar Single-Precision
Rounds low float according to immediate mode.
Pseudocode Operation
mode ← imm8[1:0]; precision_exception_suppress ← imm8[2]; xmm1[0:31] ← round(src[0:31], mode, precision_exception_suppress); xmm1[32:127] ← xmm1[32:127];Example
Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Related
More in SSE4.1
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F 3A 0A /r ib | ROUNDSS xmm1, xmm2/m32, imm8 | RMI | V/V | SSE4_1 | Round the low packed single precision floatingpoint value in xmm2/m32 and place the result in xmm1. The rounding mode is determined by imm8. |
| VEX.LIG.66.0F3A.WIG 0A /r ib | VROUNDSS xmm1, xmm2, xmm3/m32, imm8 | AVX | RVMI V/V Round the low packed single precision floatingpoint value in xmm3/m32 and place the result in xmm1. The rounding mode is determined by imm8. Also, upper packed single precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32]. |
Description
Round the single precision floating-point value in the lowest dword of the source operand (second operand) using the rounding mode specified in the immediate operand (third operand) and place the result in the destination operand (first operand). The rounding process rounds a single precision floating-point input to an integer value and returns the result as a single precision floating-point value in the lowest position. The upper three single precision floating-point values in the destination are retained. The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before rounding. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL1:32) of the corresponding YMM destination register remain unchanged. VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.
Operation
IF (imm[2] = ‘1) THEN // rounding mode is determined by MXCSR.RC DEST[31:0] := ConvertSPFPToInteger_M(SRC[31:0]); ELSE // rounding mode is determined by IMM8.RC DEST[31:0] := ConvertSPFPToInteger_Imm(SRC[31:0]); FI; DEST[127:32] remains unchanged ; ROUNDSS (128-bit Legacy SSE Version) DEST[31:0] := RoundToInteger(SRC[31:0], ROUND_CONTROL) DEST[MAXVL-1:32] (Unmodified) VROUNDSS (VEX.128 Encoded Version) DEST[31:0] := RoundToInteger(SRC2[31:0], ROUND_CONTROL) DEST[127:32] := SRC1[127:32] DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
ROUNDSS __m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode); ROUNDSS __m128 mm_floor_ss(__m128 dst, __m128 s1); ROUNDSS __m128 mm_ceil_ss(__m128 dst, __m128 s1);