invlpga

Invalidate TLB Entry in ASID

INVLPGA

Invalidates TLB entry for specific ASID (AMD SVM).

Pseudocode Operation

TLB_entry ← invalidate(RAX, ECX); // Invalidate TLB with ASID

Encoding

Binary Layout

0F

+0

01

+1

DF

+2

 

Format SVM

Opcode 0F 01 DF

Extension SVM

Operands

Related

More in SVM

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ AMD APM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
0F 01 DF	INVLPGA				Invalidates the TLB mapping for the page containing the address in rAX, for the address space identified by ECX.

Description

Invalidates the TLB entry (or entries) for the page containing the address in rAX, in the address space specified by the ASID in ECX. Used by hypervisors to invalidate guest TLB mappings when managing nested paging. Privileged; available only when SVM is enabled.