invvpid

Invalidate Translations Based on VPID

INVVPID r64, m128

Invalidates TLB entries based on Virtual Processor ID.

Details

The Invalidate Translations Based on VPID instruction invalidates TLB entries based on Virtual Processor ID.

Pseudocode Operation

// Invalidates TLB entries based on Virtual Processor ID

Example

INVVPID rax, [rbp-16]

Encoding

Binary Layout
66
+0
0F
+1
38
+2
81
+3
 
Format VMX
Opcode 66 0F 38 81
Extension VMX (VPID)

Operands

  • dest
    64-bit general-purpose register (e.g. RAX)
  • src
    128-bit memory operand