invvpid

Invalidate Translations Based on VPID

INVVPID r64, m128

Invalidates TLB entries based on Virtual Processor ID.

Details

Invalidates TLB entries based on Virtual Processor ID (VPID). The destination register specifies the invalidation type (1=individual address, 2=single VPID context, 3=all VPID contexts, 4=individual address keeping globals), and the source memory operand contains VPID and address information. CF/ZF flags indicate success or error; this instruction serializes execution.

Pseudocode Operation

if (VPID_enabled && VMX_mode_active) {
  invalidation_type ← dest;
  descriptor ← [src];
  if (invalidation_type == 1) {
    invalidate_TLB_address(descriptor);
  } else if (invalidation_type == 2) {
    invalidate_TLB_VPID(descriptor);
  } else if (invalidation_type == 3) {
    invalidate_all_TLB();
  } else if (invalidation_type == 4) {
    invalidate_TLB_address_keep_global(descriptor);
  }
  CF ← 0;
  ZF ← 0;
} else {
  CF ← 1;
  ZF ← 1;
}

Example

INVVPID rax, [rbp-16]

Encoding

Binary Layout

Format VMX

Opcode 66 0F 38 81

Extension VMX (VPID)

Operands

dest
64-bit general-purpose register (e.g. RAX)
src
128-bit memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
66 0F 38 81	INVVPID r64, m128	RM			Invalidates entries in the TLBs and paging-structure caches based on VPID (in 64-bit mode).
66 0F 38 81	INVVPID r32, m128	RM			Invalidates entries in the TLBs and paging-structure caches based on VPID (outside 64-bit mode).

Description

Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on virtualprocessor identifier (VPID). (See Chapter 31, “VMX Support for Address Translation.”) Invalidation is based on the INVVPID type specified in the register operand and the INVVPID descriptor specified in the memory operand. Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D; in 64-bit mode, the register operand has 64 bits (the instruction cannot be executed in compatibility mode). The INVVPID types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see Appendix A, “VMX Capability Reporting Facility”). There are four INVVPID types currently defined: • Individual-address invalidation: If the INVVPID type is 0, the logical processor invalidates mappings for the linear address and VPID specified in the INVVPID descriptor. In some cases, it may invalidate mappings for other linear addresses (or other VPIDs) as well. • Single-context invalidation: If the INVVPID type is 1, the logical processor invalidates all mappings tagged with the VPID specified in the INVVPID descriptor. In some cases, it may invalidate mappings for other VPIDs as well. • All-contexts invalidation: If the INVVPID type is 2, the logical processor invalidates all mappings tagged with all VPIDs except VPID 0000H. In some cases, it may invalidate translations with VPID 0000H as well. • Single-context invalidation, retaining global translations: If the INVVPID type is 3, the logical processor invalidates all mappings tagged with the VPID specified in the INVVPID descriptor except global translations. In some cases, it may invalidate global translations (and mappings with other VPIDs) as well. See the “Caching Translation Information” section in Chapter 5 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information about global translations. If an unsupported INVVPID type is specified, the instruction fails. INVVPID invalidates all the specified mappings for the indicated VPID(s) regardless of the EPTP and PCID values with which those mappings may be associated. The INVVPID descriptor comprises 128 bits and consists of a VPID and a linear address as shown in Figure 33-2. 127 64 63 16 15 0 Linear Address Reserved (must be zero) VPID Figure 33-2. INVVPID Descriptor

Operation

IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
THEN #UD;
ELSIF in VMX non-root operation
THEN VM exit;
ELSIF CPL > 0
THEN #GP(0);
ELSE
INVVPID_TYPE := value of register operand;
IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support
INVVPID_TYPE
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE           // INVVPID_TYPE must be in the range 0–3
INVVPID_DESC := value of memory operand;
IF INVVPID_DESC[63:16] ≠ 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
CASE INVVPID_TYPE OF
0:                     // individual-address invalidation
VPID := INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
GL_ADDR := INVVPID_DESC[127:64];
IF (GL_ADDR is not in a canonical form)
THEN
VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate mappings for GL_ADDR tagged with VPID;
VMsucceed;
FI;
FI;
BREAK;
1:                     // single-context invalidation
VPID := INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate all mappings tagged with VPID;
VMsucceed;
FI;
BREAK;
2:                     // all-context invalidation
Invalidate all mappings tagged with all non-zero VPIDs;
VMsucceed;
BREAK;
3:                     // single-context invalidation retaining globals
VPID := INVVPID_DESC[15:0];
IF VPID = 0
THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE
Invalidate all mappings tagged with VPID except global translations;
VMsucceed;


INVVPID— Invalidate Translations Based on VPID                                                                          33-7  Vol. 3C


FI;
BREAK;
ESAC;
FI;
FI;
FI;

Flags Affected

See the operation section and Section 33.2.

Exceptions

Protected Mode Exceptions

#GP(0) If the current privilege level is not 0. If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains an unusable segment. If the source operand is located in an execute-only code segment. #PF(fault-code) If a page fault occurs in accessing the memory operand. #SS(0) If the memory operand effective address is outside the SS segment limit. If the SS register contains an unusable segment. #UD If not in VMX operation. If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0). If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).

Real-Address Mode Exceptions

#UD The INVVPID instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD The INVVPID instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD The INVVPID instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#GP(0) If the current privilege level is not 0. If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs in accessing the memory operand. #SS(0) If the memory destination operand is in the SS segment and the memory address is in a non- canonical form. #UD If not in VMX operation. If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0). If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).