kunpckwd

Unpack and Interleave Masks Word to Doubleword

KUNPCKWD k1, k2, k3

Interleaves 16-bit masks into 32-bit mask.

Details

Unpacks and interleaves two 16-bit mask registers into a 32-bit mask register, with src2 supplying the high 16 bits and src1 supplying the low 16 bits of the result. This instruction is part of AVX-512BW and operates only on opmask registers (k0–k7); it does not modify any EFLAGS flags. The opmask register k0 cannot be used as a write mask.

Pseudocode Operation

dest[15:0] ← src1[15:0]; dest[31:16] ← src2[15:0]; dest[63:32] ← 0;

Example

KUNPCKWD k1, k2, k3

Encoding

Binary Layout
EVEX
+0
0F
+4
4B
+5
 
Format EVEX
Opcode VEX.L1.0F.W0 4B /r
Extension AVX-512BW

Operands

  • dest
    AVX-512 opmask register (k0-k7)
  • src1
    AVX-512 opmask register (k0-k7)
  • src2
    AVX-512 opmask register (k0-k7)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.L1.66.0F.W0 4B /r KUNPCKBW k1, k2, k3 V/V RVR AVX512F OR AVX10.1 Unpack 8-bit masks in k2 and k3 and write word result in k1.
VEX.L1.0F.W0 4B /r KUNPCKWD k1, k2, k3 V/V RVR AVX512BW OR AVX10.1 Unpack 16-bit masks in k2 and k3 and write doubleword result in k1.
VEX.L1.0F.W1 4B /r KUNPCKDQ k1, k2, k3 V/V RVR AVX512BW OR AVX10.1 Unpack 32-bit masks in k2 and k3 and write quadword result in k1.

Description

Unpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first operand (destination operand), starting from the low bytes. The result is zero-extended in the destination.

Operation

KUNPCKBW
DEST[7:0] := SRC2[7:0]
DEST[15:8] := SRC1[7:0]
DEST[MAX_KL-1:16] := 0

KUNPCKWD
DEST[15:0] := SRC2[15:0]
DEST[31:16] := SRC1[15:0]
DEST[MAX_KL-1:32] := 0

KUNPCKDQ
DEST[31:0] := SRC2[31:0]
DEST[63:32] := SRC1[31:0]
DEST[MAX_KL-1:64] := 0

Intel C/C++ Compiler Intrinsic Equivalent

KUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);
KUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);
KUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers Vol. 2A 3-529