bzhi

Zero High Bits Starting with Specified Bit Position

BZHI r32, r/m32, r32

Clears high bits starting at index.

Details

Zero High Bits Starting with Specified Bit Position clears all bits in the source operand at positions greater than or equal to the bit index specified in the third operand, storing the result in the destination. No flags are modified. Supported in 32-bit and 64-bit modes with BMI2 extension; the operand size can be 32 or 64 bits.

Pseudocode Operation

count ← src2[7:0] & 0x3F; mask ← (1 << count) - 1; dest ← src1 & mask;

Example

BZHI eax, ebx, eax

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.0F38.W0 F5 /r
Extension BMI2

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src1
    32-bit register or memory
  • src2
    32-bit general-purpose register (e.g. EAX)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.0F38.W0 F5 /r BZHI r32a, r/m32, r32b RMV V/V BMI2 Zero bits in r/m32 starting with the position in r32b, write result to r32a.
VEX.LZ.0F38.W1 F5 /r BZHI r64a, r/m64, r64b RMV V/N.E. BMI2 Zero bits in r/m64 starting with the position in r64b, write result to r64a.

Description

BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first operand) and clears the higher bits in the destination according to the INDEX value specified by the second source operand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand is greater than OperandSize -1. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

N := SRC2[7:0]
DEST := SRC1
IF (N < OperandSize)
DEST[OperandSize-1:N] := 0
FI
IF (N > OperandSize - 1)
CF := 1
ELSE
CF := 0
FI

Intel C/C++ Compiler Intrinsic Equivalent

BZHI unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);
BZHI unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);

Flags Affected

ZF and SF flags are updated based on the result. CF flag is set as specified in the Operation section. OF flag is cleared. AF and PF flags are undefined.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” BZHI—Zero High Bits Starting with Specified Bit Position Vol. 2A 3-120