fld1

Load Constant 1.0

FLD1

Pushes +1.0 onto the FPU register stack.

Details

Decrements the FPU stack pointer (ST(7)→ST(0)), then loads the constant +1.0 (extended precision double) into the top of the x87 FPU register stack (ST(0)). The instruction sets the C1 flag to 0 and leaves other status flags unchanged unless a stack overflow occurs (C0, C2, C3 may be set on exception). No CPU integer flags are affected.

Pseudocode Operation

FPU_TOP ← FPU_TOP - 1;
if (FPU_TOP overflow) {
  raise FPU_EXCEPTION;
}
ST(0) ← +1.0;

Example

FLD1

Encoding

Binary Layout
D9
+0
E8
+1
 
Format Legacy
Opcode D9 E8
Extension x87 FPU

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
D9 E8 FLD1 Valid Valid Push +1.0 onto the FPU register stack.
D9 E9 FLDL2T Valid Valid Push log210 onto the FPU register stack.
D9 EA FLDL2E Valid Valid Push log2e onto the FPU register stack.
D9 EB FLDPI Valid Valid Push π onto the FPU register stack.
D9 EC FLDLG2 Valid Valid Push log102 onto the FPU register stack.
D9 ED FLDLN2 Valid Valid Push loge2 onto the FPU register stack.
D9 EE FLDZ Valid Valid Push +0.0 onto the FPU register stack.

Description

Push one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, π, log102, and loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control word) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. See the section titled “Approximation of Pi” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the π constant. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility When the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel 8087 and Intel 287 math coprocessors.

Operation

TOP := TOP − 1;
ST(0) := CONSTANT;

Exceptions

Protected Mode Exceptions

#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode. FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant Vol. 2A 3-354 Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode. FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant Vol. 2A 3-355