pfadd
Packed Floating-Point Add
PFADD mm, mm/m64
Adds two packed floats (3DNow!).
Details
Adds two packed single-precision floating-point values (two 32-bit floats per 64-bit operand) using 3DNow! arithmetic. The result is written to the destination MMX register with round-to-nearest mode. This instruction does not modify EFLAGS; floating-point exceptions may be masked or pending.
Pseudocode Operation
dest[31:0] ← float_add(dest[31:0], src[31:0]); dest[63:32] ← float_add(dest[63:32], src[63:32]);Example
PFADD mm, mm/m64
Encoding
Binary Layout
0F
+0
0F
+1
ModRM
+2
9E
+3
Operands
-
dest
64-bit MMX register -
src
64-bit MMX register or Memory operand
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| D8 /0 | FADD m32fp | Valid Valid | Add m32fp to ST(0) and store result in ST(0). | ||
| DC /0 | FADD m64fp | Valid Valid | Add m64fp to ST(0) and store result in ST(0). | ||
| D8 C0+i | FADD ST(0), ST(i) | Valid Valid | Add ST(0) to ST(i) and store result in ST(0). | ||
| DC C0+i | FADD ST(i), ST(0) | Valid Valid | Add ST(i) to ST(0) and store result in ST(i). | ||
| DE C0+i | FADDP ST(i), ST(0) | Valid Valid | Add ST(0) to ST(i), store result in ST(i), and pop the register stack. | ||
| DE C1 | FADDP | Valid Valid | Add ST(0) to ST(1), store result in ST(1), and pop the register stack. | ||
| DA /0 | FIADD m32int | Valid Valid | Add m32int to ST(0) and store result in ST(0). | ||
| DE /0 | FIADD m16int | Valid Valid | Add m16int to ST(0) and store result in ST(0). |
Description
Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single precision or double precision floating-point format or in word or doubleword integer format.
The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The oneoperand version adds the contents of a memory location (either a floating-point or an integer value) to the contents of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice versa. The value in ST(0) can be doubled by coding:
FADD ST(0), ST(0);
The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. (The no-operand version of the floating-point add instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)
The FIADD instructions convert an integer source operand to double extended-precision floating-point format before performing the addition.
The table on the following page shows the results obtained when adding various classes of numbers, assuming that neither overflow nor underflow occurs.
When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward −∞ mode, in which case the result is −0. When the source operand is an integer 0, it is treated as a +0.
When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infinities of opposite signs, an invalid-operation exception is generated. See Table 3-20.
FADD/FADDP/FIADD—Add Vol. 2A 3-311
Table 3-20. FADD/FADDP/FIADD Results
DEST
− ∞ − F − 0 + 0 + F + ∞ NaN
− ∞ − ∞ − ∞ − ∞ − ∞ − ∞ * NaN
− F or − I − ∞ − F SRC SRC ± F or ± 0 + ∞ NaN
SRC −0 − ∞ DEST − 0 ± 0 DEST + ∞ NaN
+ 0 − ∞ DEST ± 0 + 0 DEST + ∞ NaN
+ F or + I − ∞ ± F or ± 0 SRC SRC + F + ∞ NaN
+ ∞ * + ∞ + ∞ + ∞ + ∞ + ∞ NaN
NaN NaN NaN NaN NaN NaN NaN NaN
Operation
IF Instruction = FIADD THEN DEST := DEST + ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* Source operand is floating-point value *) DEST := DEST + SRC; FI; IF Instruction = FADDP THEN PopRegisterStack; FI;
Exceptions
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#UD If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used.
FADD/FADDP/FIADD—Add Vol. 2A 3-313