lidt

Load Interrupt Descriptor Table Register

LIDT m16&32

Loads the IDT register (Privileged).

Details

Loads the Interrupt Descriptor Table (IDT) register with a limit (16 bits) and base address (32 bits in 32-bit mode, 64 bits in 64-bit mode) from a 6-byte or 10-byte memory operand. This is a privileged instruction (requires CPL=0) and causes a pipeline flush. No flags are affected. In 64-bit mode, the operand is 10 bytes (16-bit limit + 64-bit base).

Pseudocode Operation

IDTR.limit ← [m16&32 + 0:1]
IDTR.base ← [m16&32 + 2:5]  // 32-bit or 64-bit depending on mode

Example

LIDT m16&32

Encoding

Binary Layout

ModRM

Format System

Opcode 0F 01 /3

Extension System

Operands

src
Memory

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
0F 01 /2	LGDT m16&32	M	N.E. Valid	Load m into GDTR.
0F 01 /3	LIDT m16&32	M	N.E. Valid	Load m into IDTR.
0F 01 /2	LGDT m16&64	M	Valid N.E.	Load m into GDTR.
0F 01 /3	LIDT m16&64	M	Valid N.E.	Load m into IDTR.

Description

Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is filled with zeros. The LGDT and LIDT instructions are used only in operating-system software; they are not used in application programs. They are the only instructions that directly load a linear address (that is, not a segment-relative address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode. In 64-bit mode, the instruction’s operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the summary chart at the beginning of this section for encoding data and limits. See “SGDT—Store Global Descriptor Table Register” in Chapter 4, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR. LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Vol. 2A 3-553

Operation

IF Instruction is LIDT
THEN
IF OperandSize = 16
THEN
IDTR(Limit) := SRC[0:15];
IDTR(Base) := SRC[16:47] AND 00FFFFFFH;
ELSE IF 32-bit Operand Size
THEN
IDTR(Limit) := SRC[0:15];
IDTR(Base) := SRC[16:47];
FI;
ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
THEN
IDTR(Limit) := SRC[0:15];
IDTR(Base) := SRC[16:79];
FI;
FI;
ELSE (* Instruction is LGDT *)
IF OperandSize = 16
THEN
GDTR(Limit) := SRC[0:15];
GDTR(Base) := SRC[16:47] AND 00FFFFFFH;
ELSE IF 32-bit Operand Size
THEN
GDTR(Limit) := SRC[0:15];
GDTR(Base) := SRC[16:47];
FI;
ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
THEN
GDTR(Limit) := SRC[0:15];
GDTR(Base) := SRC[16:79];
FI;
FI;
FI;

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#UD If the LOCK prefix is used. #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Vol. 2A 3-554

Real-Address Mode Exceptions

#UD If the LOCK prefix is used. #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions

#UD If the LOCK prefix is used. #GP If the current privilege level is not 0.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the current privilege level is not 0. If the memory address is in a non-canonical form. #UD If the LOCK prefix is used. #PF(fault-code) If a page fault occurs. LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Vol. 2A 3-555