blsr

Reset Lowest Set Bit

BLSR r32, r/m32

Clears the lowest set bit (x & (x-1)).

Details

Clears the lowest set bit in src by computing (src & (src - 1)), storing the result in dest. ZF is set if the result is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

Pseudocode Operation

dest ← src & (src - 1)
ZF ← (dest == 0)
CF ← (src == 0)
OF ← 0
AF ← undefined
PF ← undefined

Example

BLSR eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.0F38.W0 F3 /1
Extension BMI1

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.0F38.W0 F3 /1 BLSR r32, r/m32 VM V/V BMI1 Reset lowest set bit of r/m32, keep all other bits of r/m32 and write result to r32.
VEX.LZ.0F38.W1 F3 /1 BLSR r64, r/m64 VM V/N.E. BMI1 Reset lowest set bit of r/m64, keep all other bits of r/m64 and write result to r64.

Description

Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destination operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets CF. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp := (SRC-1) bitwiseAND ( SRC );
SF := temp[OperandSize -1];
ZF := (temp = 0);
IF SRC = 0
CF := 1;
ELSE
CF := 0;
FI
DEST := temp;

Intel C/C++ Compiler Intrinsic Equivalent

BLSR unsigned __int32 _blsr_u32(unsigned __int32 src);
BLSR unsigned __int64 _blsr_u64(unsigned __int64 src);

Flags Affected

ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags are undefined.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” BLSR—Reset Lowest Set Bit Vol. 2A 3-89