movmskpd

Extract Packed Double-Precision Mask

MOVMSKPD r32, xmm

Extracts sign bits from two doubles into low 2 bits of register.

Details

Extracts the sign bit (bit 63) from each of two packed double-precision floating-point values in an XMM register and packs them into the low 2 bits of a general-purpose 32-bit register. The upper 30 bits of the destination are cleared. No flags are modified.

Pseudocode Operation

dest ← 0; dest[0] ← src[63]; dest[1] ← src[127];

Example

MOVMSKPD eax, xmm0

Encoding

Binary Layout
66
+0
0F
+1
50
+2
 
Format SSE2
Opcode 66 0F 50
Extension SSE2

Operands

  • dest
    Reg
  • src
    XMM

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
66 0F 50 /r MOVMSKPD reg, xmm RM V/V SSE2 Extract 2-bit sign mask from xmm and store in reg. The upper bits of r32 or r64 are filled with zeros.
VEX.128.66.0F.WIG 50 /r VMOVMSKPD reg, xmm2 RM V/V AVX Extract 2-bit sign mask from xmm2 and store in reg. The upper bits of r32 or r64 are zeroed.
VEX.256.66.0F.WIG 50 /r VMOVMSKPD reg, ymm2 RM V/V AVX Extract 4-bit sign mask from ymm2 and store in reg. The upper bits of r32 or r64 are zeroed.

Description

Extracts the sign bits from the packed double precision floating-point values in the source operand (second operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored in the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode. 128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register. VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose register. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

(V)MOVMSKPD (128-bit Versions)
DEST[0] := SRC[63]
DEST[1] := SRC[127]
IF DEST = r32
THEN DEST[31:2] := 0;
ELSE DEST[63:2] := 0;
FI

VMOVMSKPD (VEX.256 Encoded Version)
DEST[0] := SRC[63]
DEST[1] := SRC[127]
DEST[2] := SRC[191]
DEST[3] := SRC[255]
IF DEST = r32
THEN DEST[31:4] := 0;
ELSE DEST[63:4] := 0;
FI





MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask                                                                         Vol. 2B 4-85

Intel C/C++ Compiler Intrinsic Equivalent

MOVMSKPD int _mm_movemask_pd ( __m128d a)
VMOVMSKPD _mm256_movemask_pd(__m256d a)

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-24, “Type 7 Class Exception Conditions,” additionally: #UD If VEX.vvvv ≠ 1111B. MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask Vol. 2B 4-86