hreset

History Reset

HRESET imm8

Resets processor history (prediction) structures.

Details

Resets selected processor prediction/history structures (BTB, TLB, or other micro-architectural caches) as specified by the 8-bit immediate operand. The instruction may serialize the execution pipeline and is typically used to mitigate side-channel attacks. No EFLAGS are modified; the instruction requires HRESET CPU feature support.

Pseudocode Operation

IF CPUID.HRESET = 0 THEN #UD FI;
select_bits ← imm8[7:0];
IF select_bits & 0x01 THEN RESET_BTB() FI;
IF select_bits & 0x02 THEN RESET_TLB() FI;
IF select_bits & 0x04 THEN RESET_RSB() FI;

Example

HRESET 3

Encoding

Binary Layout
F3
+0
0F
+1
3A
+2
F0
+3
 
Format Legacy
Opcode F3 0F 3A F0 C0 ib
Extension HRESET

Operands

  • dest
    8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
F3 0F 3A F0 C0 /ib HRESET A V/V Processor history reset request. Controlled by the HRESET imm8, <EAX> EAX implicit operand.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:r/m (r) N/A N/A N/A

Description

Requests the processor to selectively reset selected components of hardware history maintained by the current logical processor. HRESET operation is controlled by the implicit EAX operand. The value of the explicit imm8 operand is ignored. This instruction can only be executed at privilege level 0. The HRESET instruction can be used to request reset of multiple components of hardware history. Prior to the execution of HRESET, the system software must take the following steps: 1. Enumerate the HRESET capabilities via CPUID.20H.00H:EBX, which indicates what components of hardware history can be reset. 2. Only the bits enumerated by CPUID.20H.00H:EBX can be set in the IA32_HRESET_ENABLE MSR. HRESET causes a general-protection exception (#GP) if EAX sets any bits that are not set in the IA32_HRESET_ENABLE MSR. Any attempt to execute the HRESET instruction inside a transactional region will result in a transaction abort.

Operation

IF EAX = 0
THEN NOP
ELSE
FOREACH i such that EAX[i] = 1
Reset prediction history for feature i
FI

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#GP(0) If CPL > 0 or (EAX AND NOT IA32_HRESET_ENABLE) ≠0. #UD If CPUID.07H.01H:EAX.HRESET[22] = 0.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

#GP(0) HRESET instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode. HRESET—History Reset Vol. 2A 3-440

64-Bit Mode Exceptions

Same exceptions as in protected mode. HRESET—History Reset Vol. 2A 3-441