blsic

Bit Line Set Isolated and Complement

BLSIC r32, r/m32

Isolates lowest set bit and complements (~x | (x-1)).

Details

Isolates the lowest set bit and complements the result, computing ~src | (src - 1). This TBM instruction is useful for extracting bit masks and operates on 32-bit operands in protected/64-bit modes. No flags are modified by this instruction.

Pseudocode Operation

dest ← ~src | (src - 1)

Example

BLSIC eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format TBM
Opcode XOP.L0.09.W0 01 /6
Extension TBM

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.0F38.W0 F3 /3 BLSI r32, r/m32 VM V/V BMI1 Extract lowest set bit from r/m32 and set that bit in r32.
VEX.LZ.0F38.W1 F3 /3 BLSI r64, r/m64 VM V/N.E. BMI1 Extract lowest set bit from r/m64, and set that bit in r64.

Description

Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in the destination to 0 and sets ZF and CF. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp := (-SRC) bitwiseAND (SRC);
SF := temp[OperandSize -1];
ZF := (temp = 0);
IF SRC = 0
CF := 0;
ELSE
CF := 1;
FI
DEST := temp;

Intel C/C++ Compiler Intrinsic Equivalent

BLSI unsigned __int32 _blsi_u32(unsigned __int32 src);
BLSI unsigned __int64 _blsi_u64(unsigned __int64 src);

Flags Affected

ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF flags are undefined.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” BLSI—Extract Lowest Set Isolated Bit Vol. 2A 3-87