pfrcp
Packed Floating-Point Reciprocal
PFRCP mm, mm/m64
Approximates reciprocal (3DNow!).
Details
Computes a fast approximation of the reciprocal (1/x) for each packed single-precision floating-point value using 3DNow!. The result is written to the destination MMX register with reduced precision (typically 14–15 bits of accuracy). This instruction does not modify EFLAGS; it may generate floating-point exceptions.
Pseudocode Operation
dest[31:0] ← float_reciprocal_approx(src[31:0]); dest[63:32] ← float_reciprocal_approx(src[63:32]);
Example
PFRCP mm, mm/m64
Encoding
Binary Layout
0F
+0
0F
+1
ModRM
+2
96
+3
Operands
-
dest
64-bit MMX register -
src
64-bit MMX register or Memory operand
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 0F 0F /r 96 | PFRCP mmx1, mmx2/mem64 |
Description
Computes the approximate reciprocal of the single-precision floating-point value in the low-order 32 bits of an MMX register or 64-bit memory location and writes the result in both doublewords of another MMX register. The result is accurate to 14 bits.
The PFRCP result can be forwarded to the Newton-Raphson iteration step 1 (PFRCPIT1) and NewtonRaphson iteration step 2 (PFRCPIT2) instructions to increase the accuracy of the reciprocal. The first stage of this refinement in accuracy (PFRCPIT1) requires that the input and output of the previously executed PFRCP instruction be used as input to the PFRCPIT1 instruction.
The estimate contains the correct round-to-nearest value for approximately 99% of all arguments. The remaining arguments differ from the correct round-to-nearest value for the reciprocal by 1 unit-in-thelast-place (ulp). For details, see the data sheet or other software-optimization documentation relating to particular hardware implementations.
PFRCP(x) returns 0 for x >= 2-126. The numeric range for operands is shown in Table 1-15 on page 116.
The PFRCP instruction is an AMD 3DNow!™ instruction. The presence of this instruction set is indicated by CPUID feature bits. See “CPUID” in Volume 3 for more information about the CPUID instruction.
AMD no longer recommends the use of 3DNow! instructions, which have been superceded by their more efficient 128-bit media counterparts. For a complete list of recommended instruction substitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” on page 333.
Recommended Instruction Substitution
RCPSS
Flags Affected
None 116 [AMD PublicPFRCP Use] Instruction64-BitReferenceMedia