extractps

Extract Packed Single-Precision

EXTRACTPS r32/m32, xmm1, imm8

Extracts a single float from XMM to an integer register.

Details

Extracts a single 32-bit float from a source XMM register at a lane specified by bits [1:0] of the immediate operand and writes it to a 32-bit destination (GP register or memory). The extracted value is zero-extended if written to a 32-bit register. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.

Pseudocode Operation

imm ← imm8;
index ← imm & 0x3;
src_dword ← xmm1[index*32 + 31 : index*32];
dest[31:0] ← src_dword;

Example

EXTRACTPS r32/m32, xmm1, 3

Encoding

Binary Layout
66
+0
0F
+1
3A
+2
17
+3
 
Format SSE4.1
Opcode 66 0F 3A 17
Extension SSE4.1

Operands

  • dest
    General-purpose register or Memory operand
  • src1
    128-bit XMM SIMD register
  • src2
    8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
66 0F 3A 17 /r ib EXTRACTPS reg/m32, xmm1, imm8 A VV SSE4_1 Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.
VEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8 A V/V AVX Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.
EVEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8 B V/V AVX512F OR AVX10.1 Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:r/m (w) ModRM:reg (r) imm8 N/A
B Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) imm8 N/A

Description

Extracts a single precision floating-point value from the source operand (second operand) at the 32-bit offset specified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored. The extracted single precision floating-point value is stored in the low 32-bits of the destination operand In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register are filled with zero. REX.W is ignored. VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits. VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. 128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits. The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the 32-bit floating-point value. If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception. EXTRACTPS—Extract Packed Floating-Point Values Vol. 2A 3-305

Operation

VEXTRACTPS (EVEX and VEX.128 Encoded Version)
SRC_OFFSET := IMM8[1:0]
IF (64-Bit Mode and DEST is register)
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
DEST[63:32] := 0
ELSE
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI

EXTRACTPS (128-bit Legacy SSE Version)
SRC_OFFSET := IMM8[1:0]
IF (64-Bit Mode and DEST is register)
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
DEST[63:32] := 0
ELSE
DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI

Intel C/C++ Compiler Intrinsic Equivalent

EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

VEX-encoded instructions, see Table 2-22, “Type 5 Class Exception Conditions.” EVEX-encoded instructions, see Table 2-59, “Type E9NF Class Exception Conditions.” Additionally: #UD IF VEX.L = 0. #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B. EXTRACTPS—Extract Packed Floating-Point Values Vol. 2A 3-306