dppd

Dot Product Packed Double-Precision

DPPD xmm1, xmm2/m128, imm8

Computes the dot product of two double vectors.

Details

Computes the dot product of two packed double-precision floating-point vectors (2 doubles per 128-bit operand) and stores the result in the destination. The imm8 byte controls which elements participate in the dot product and which output elements are zeroed. No flags are affected; this is a SSE4.1 instruction that operates only in 64-bit and protected modes.

Pseudocode Operation

select_mask ← imm8[7:4]
product_mask ← imm8[3:0]
temp ← 0.0
for i in 0..1:
  if (product_mask[i] == 1):
    temp ← temp + (xmm1[i*64+63:i*64] * src1[i*64+63:i*64])
for i in 0..1:
  if (select_mask[i] == 1):
    dest[i*64+63:i*64] ← temp
  else:
    dest[i*64+63:i*64] ← 0.0

Example

DPPD xmm1, xmm2/m128, 3

Encoding

Binary Layout
66
+0
0F
+1
3A
+2
41
+3
 
Format SSE4.1
Opcode 66 0F 3A 41
Extension SSE4.1

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register or Memory operand
  • src2
    8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
66 0F 3A 41 /r ib DPPD xmm1, xmm2/m128, imm8 RMI V/V SSE4_1 Selectively multiply packed double precision floating-point values from xmm1 with packed double precision floating-point values from xmm2, add and selectively store the packed double precision floating-point values to xmm1.
VEX.128.66.0F3A.WIG 41 /r ib VDPPD xmm1,xmm2, xmm3/m128, imm8 RVMI V/V AVX Selectively multiply packed double precision floating-point values from xmm2 with packed double precision floating-point values from xmm3, add and selectively store the packed double precision floating-point values to xmm1.

Description

Conditionally multiplies the packed double precision floating-point values in the destination operand (first operand) with the packed double precision floating-point values in the source (second operand) depending on a mask extracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corresponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. The two resulting double precision values are summed into an intermediate result. The intermediate result is conditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte. If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding qword element in the destination operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero. DPPD follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally generated NaNs will have at least one NaN propagated to the destination. 128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed. If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception. DPPD—Dot Product of Packed Double Precision Floating-Point Values Vol. 2A 3-277

Operation

DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
THEN Temp1[63:0] := DEST[63:0] * SRC[63:0]; // update SIMD exception flags
ELSE Temp1[63:0] := +0.0; FI;
IF (imm8[5] = 1)
THEN Temp1[127:64] := DEST[127:64] * SRC[127:64]; // update SIMD exception flags
ELSE Temp1[127:64] := +0.0; FI;
/* if unmasked exception reported, execute exception handler*/

Temp2[63:0] := Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/

IF (imm8[0] = 1)
THEN DEST[63:0] := Temp2[63:0];
ELSE DEST[63:0] := +0.0; FI;
IF (imm8[1] = 1)
THEN DEST[127:64] := Temp2[63:0];
ELSE DEST[127:64] := +0.0; FI;

DPPD (128-bit Legacy SSE Version)
DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[MAXVL-1:128] (Unmodified)

VDPPD (VEX.128 Encoded Version)
DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

DPPD __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal. Exceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the destination untouched.

Other Exceptions

See Table 2-19, “Type 2 Class Exception Conditions,” additionally: #UD If VEX.L= 1. DPPD—Dot Product of Packed Double Precision Floating-Point Values Vol. 2A 3-278