divps

Divide Packed Single-Precision

DIVPS xmm, xmm/m128

Divides four 32-bit floats.

Details

The Divide Packed Single-Precision instruction divides four 32-bit floats.

Pseudocode Operation

// Divides four 32-bit floats

Example

DIVPS xmm0, xmm1

Encoding

Binary Layout
0F
+0
5E
+1
 
Format SSE
Opcode 0F 5E
Extension SSE

Operands

  • dest
    128-bit SSE/AVX register (XMM)
  • src
    128-bit XMM register or 128-bit memory