ktestw

Test Masks Word

KTESTW k1, k2

ANDs 16-bit masks and sets EFLAGS (ZF/CF).

Details

Performs a bitwise AND of two 16-bit AVX-512 opmask registers and updates EFLAGS based on the result without storing the AND product. Sets ZF if the result is zero, clears ZF otherwise; sets CF if all bits of the first operand are zero, clears CF otherwise. This instruction executes in 64-bit mode only and is part of AVX-512F.

Pseudocode Operation

temp ← k1 AND k2
ZF ← (temp == 0)
CF ← (k1 == 0)
OF ← 0
SF ← 0
AF ← undefined
PF ← undefined

Example

KTESTW k1, k2

Encoding

Binary Layout
EVEX
+0
0F
+4
99
+5
 
Format EVEX
Opcode VEX.L0.0F.W0 99 /r
Extension AVX-512F

Operands

  • dest
    AVX-512 opmask register (k0-k7)
  • src
    AVX-512 opmask register (k0-k7)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.L0.0F.W0 99 /r KTESTW k1, k2 V/V RR AVX512DQ OR AVX10.1 Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask register sources.
VEX.L0.66.0F.W0 99 /r KTESTB k1, k2 V/V RR AVX512DQ OR AVX10.1 Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask register sources.
VEX.L0.0F.W1 99 /r KTESTQ k1, k2 V/V RR AVX512BW OR AVX10.1 Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask register sources.
VEX.L0.66.0F.W1 99 /r KTESTD k1, k2 V/V RR AVX512BW OR AVX10.1 Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask register sources.

Description

Performs a bitwise comparison of the bits of the first source operand and corresponding bits in the second source operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is clear. Only the EFLAGS register is updated. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

KTESTW
TEMP[15:0] := SRC2[15:0] AND SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN ZF :=1;
ELSE ZF := 0;
FI;
TEMP[15:0] := SRC2[15:0] AND NOT SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN CF :=1;
ELSE CF := 0;
FI;
AF := OF := PF := SF := 0;

KTESTB
TEMP[7:0] := SRC2[7:0] AND SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN ZF :=1;
ELSE ZF := 0;
FI;
TEMP[7:0] := SRC2[7:0] AND NOT SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN CF :=1;
ELSE CF := 0;
FI;
AF := OF := PF := SF := 0;



KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags                                                                     Vol. 2A 3-527
KTESTQ
TEMP[63:0] := SRC2[63:0] AND SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN ZF :=1;
ELSE ZF := 0;
FI;
TEMP[63:0] := SRC2[63:0] AND NOT SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN CF :=1;
ELSE CF := 0;
FI;
AF := OF := PF := SF := 0;

KTESTD
TEMP[31:0] := SRC2[31:0] AND SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN ZF :=1;
ELSE ZF := 0;
FI;
TEMP[31:0] := SRC2[31:0] AND NOT SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN CF :=1;
ELSE CF := 0;
FI;
AF := OF := PF := SF := 0;

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags Vol. 2A 3-528