fclex

Clear Exceptions

FCLEX

Clears floating-point exception flags.

Details

Clears all floating-point exception flags (IE, DE, ZE, OE, UE, PE) in the FPU status word without clearing the condition codes or the stack. The instruction is preceded by FWAIT (0x9B) to synchronize with any pending FPU operations. Does not affect CPU EFLAGS or FPU control/tag words.

Pseudocode Operation

FPU_Status_Word.IE ← 0;
FPU_Status_Word.DE ← 0;
FPU_Status_Word.ZE ← 0;
FPU_Status_Word.OE ← 0;
FPU_Status_Word.UE ← 0;
FPU_Status_Word.PE ← 0;

Example

FCLEX

Encoding

Binary Layout
9B
+0
DB
+1
E2
+2
 
Format Legacy
Opcode 9B DB E2
Extension x87 FPU

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
9B DB E2 FCLEX Valid Valid Clear floating-point exception flags after checking for pending unmasked floating-point exceptions.
DB E2 FNCLEX1 Valid Valid Clear floating-point exception flags without checking for pending unmasked floating-point exceptions.

Description

Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does not. The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An FNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 processor. This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point exception flags in the MXCSR register. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

FPUStatusWord[0:7] := 0;
FPUStatusWord[15] := 0;

Exceptions

Protected Mode Exceptions

#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode. FCLEX/FNCLEX—Clear Exceptions Vol. 2A 3-320

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode. FCLEX/FNCLEX—Clear Exceptions Vol. 2A 3-321