vrcp14ps

Compute Approximate Reciprocal (14-bit)

VRCP14PS zmm1 {k1}, zmm2/m512

Approximate 1/x with 2^-14 error.

Details

Computes a 14-bit reciprocal approximation (1/x) for each single-precision float in the source operand, writing results to the destination with a maximum relative error of 2^-14. The instruction operates on 512-bit vectors (16 × 32-bit floats) in AVX-512, supports writemask control via k1, and sets no CPU flags. Denormalized inputs produce denormalized outputs; NaN, zero, and infinity operands behave according to IEEE 754 semantics.

Pseudocode Operation

for i = 0 to 15:
  if k1[i] or no mask:
    zmm1[32*i+31:32*i] ← approximate_reciprocal_14bit(zmm2/m512[32*i+31:32*i])
  else if zeroing:
    zmm1[32*i+31:32*i] ← 0

Example

VRCP14PS zmm1, zmm2/m512

Encoding

Binary Layout

EVEX

Format EVEX

Opcode EVEX.512.66.0F38.W0 4C /r

Extension AVX-512F

Operands

dest
512-bit ZMM AVX-512 register
src
512-bit ZMM AVX-512 register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
EVEX.128.66.0F38.W0 4C /r	VRCP14PS xmm1 {k1}{z}, xmm2/m128/m32bcst	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Computes the approximate reciprocals of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the results in xmm1. Under writemask.
EVEX.256.66.0F38.W0 4C /r	VRCP14PS ymm1 {k1}{z}, ymm2/m256/m32bcst	A	V/V	(AVX512VL AND AVX512F) OR AVX10.1	Computes the approximate reciprocals of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask.
EVEX.512.66.0F38.W0 4C /r	VRCP14PS zmm1 {k1}{z}, zmm2/m512/m32bcst	A	V/V	AVX512F OR AVX10.1	Computes the approximate reciprocals of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	Full	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the packed single precision floating-point values in the source operand (the second operand) and stores the packed single precision floatingpoint results in the destination operand (the first operand). The maximum relative error for this approximation is less than 2-14. The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask. The VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e., not as a 0.0). Underflow results are flushed to zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e., correct underflow result is written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported. Table 5-25. VRCP14PS/VRCP14SS Special Cases Input value Result value Comments 0 ≤ X ≤ 2-128 INF Very small denormal -2-128 ≤ X ≤ -0 -INF Very small denormal X > 2126 Underflow Up to 18 bits of fractions are returned1 X < -2126 -Underflow Up to 18 bits of fractions are returned1 X = 2-n 2n X = -2-n -2n

Operation

VRCP14PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN DEST[i+31:i] := APPROXIMATE(1.0/SRC[31:0]);
ELSE DEST[i+31:i] := APPROXIMATE(1.0/SRC[i+31:i]);
FI;
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE                                                         ; zeroing-masking
DEST[i+31:i] := 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VRCP14PS __m512 _mm512_rcp14_ps( __m512 a);
VRCP14PS __m512 _mm512_mask_rcp14_ps(__m512 s, __mmask16 k, __m512 a);
VRCP14PS __m512 _mm512_maskz_rcp14_ps( __mmask16 k, __m512 a);
VRCP14PS __m256 _mm256_rcp14_ps( __m256 a);
VRCP14PS __m256 _mm512_mask_rcp14_ps(__m256 s, __mmask8 k, __m256 a);
VRCP14PS __m256 _mm512_maskz_rcp14_ps( __mmask8 k, __m256 a);
VRCP14PS __m128 _mm_rcp14_ps( __m128 a);
VRCP14PS __m128 _mm_mask_rcp14_ps(__m128 s, __mmask8 k, __m128 a);
VRCP14PS __m128 _mm_maskz_rcp14_ps( __mmask8 k, __m128 a);

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, “Type E4 Class Exception Conditions.” VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values Vol. 2C 5-677