vphaddbw
Vector Packed Horizontal Add Byte to Word
VPHADDBW xmm1, xmm2/m128
Adds adjacent bytes to words.
Details
Horizontally adds adjacent pairs of signed 8-bit bytes from xmm2/m128, accumulating results as 16-bit words in xmm1. Each pair of bytes produces one 16-bit word result; the operation doubles the data width. This XOP extension instruction does not affect EFLAGS and handles signed arithmetic with saturation or wrapping semantics dependent on implementation.
Pseudocode Operation
for i = 0 to 7 {
xmm1[16*i:16*i+15] ← sign_extend(xmm2/m128[8*(2*i):8*(2*i)+7]) + sign_extend(xmm2/m128[8*(2*i+1):8*(2*i+1)+7])
}Example
VPHADDBW xmm1, xmm2/m128
Encoding
Binary Layout
VEX
+0
opcode
+3
ModRM
+4
Operands
-
dest
128-bit XMM SIMD register -
src
128-bit XMM SIMD register or Memory operand
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.1111.0.00 C1 /r | VPHADDBW xmm1, xmm2/mem128 |
Description
Signed Byte to Signed Word
Adds each adjacent pair of 8-bit signed integer values of the source and packs the sign-extended 16bit integer result of each addition into the corresponding word element of the destination.
There are two operands: VPHADDBW dest, src
The destination is an XMM register and the source is either an XMM register or a 128-bit memory location. Bits [255:128] of the corresponding YMM register are cleared.
Flags Affected
None None
Exceptions
Exceptions
Mode
Exception Cause of Exception
Real Virt Prot
X Instruction not supported, as indicated by CPUID feature identifier.
X X XOP instructions are only recognized in protected mode.
X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE].
X XFEATURE_ENABLED_MASK[2:1] ! = 11b.
Invalid opcode, #UD X XOP.W = 1.
A XOP.vvvv ! = 1111b.
X XOP.L = 1.
X REX, F2, F3, or 66 prefix preceding XOP prefix.
X Lock prefix (F0h) preceding opcode.
Device not available, #NM X CR0.TS = 1.
Stack, #SS X Memory address exceeding stack segment limit or non-canonical.
X Memory address exceeding data segment limit or non-canonical.
General protection, #GP
X Null data segment used to reference memory.
Page fault, #PF X Instruction execution caused a page fault.
Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled.
X — XOP exception
766 [AMDVPHADDBWPublic Use] Instruction Reference