blendpd

Blend Packed Double-Precision

BLENDPD xmm1, xmm2/m128, imm8

Selects doubles from two sources based on immediate mask.

Details

Selects each 64-bit double-precision element from the destination or source register based on the corresponding bit in an 8-bit immediate mask (bit 0 for element 0, bit 1 for element 1). If the bit is 0, the element from xmm1 is retained; if 1, the element from the source is used. No CPU flags are affected by this SIMD operation, which is part of the SSE4.1 extension.

Pseudocode Operation

imm ← imm8;
xmm1[63:0] ← (imm[0] == 1) ? src[63:0] : xmm1[63:0];
xmm1[127:64] ← (imm[1] == 1) ? src[127:64] : xmm1[127:64];

Example

BLENDPD xmm1, xmm2/m128, 3

Encoding

Binary Layout

Format SSE4.1

Opcode 66 0F 3A 0D

Extension SSE4.1

Operands

dest
128-bit XMM SIMD register
src1
128-bit XMM SIMD register or Memory operand
src2
8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
66 0F 3A 0D /r ib	BLENDPD xmm1, xmm2/m128, imm8	RMI	V/V	SSE4_1	Select packed double precision floating-point values from xmm1 and xmm2/m128 from mask specified in imm8 and store the values into xmm1.
VEX.128.66.0F3A.WIG 0D /r ib	VBLENDPD xmm1, xmm2, xmm3/m128, imm8			AVX	RVMI V/V Select packed double precision floating-point Values from xmm2 and xmm3/m128 from mask in imm8 and store the values in xmm1.
VEX.256.66.0F3A.WIG 0D /r ib	VBLENDPD ymm1, ymm2, ymm3/m256, imm8			AVX	RVMI V/V Select packed double precision floating-point Values from ymm2 and ymm3/m256 from mask in imm8 and store the values in ymm1.

Description

Double precision floating-point values from the second source operand (third operand) are conditionally merged with values from the first source operand (second operand) and written to the destination operand (first operand). The immediate bits [3:0] determine whether the corresponding double precision floating-point value in the destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is ”1”, then the double precision floating-point value in the second source operand is copied, else the value in the first source operand is copied. 128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. VEX.128 encoded version: the first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.

Operation

BLENDPD (128-bit Legacy SSE Version)
IF (IMM8[0] = 0)THEN DEST[63:0] := DEST[63:0]
ELSE DEST [63:0] := SRC[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] := DEST[127:64]
ELSE DEST [127:64] := SRC[127:64] FI
DEST[MAXVL-1:128] (Unmodified)

VBLENDPD (VEX.128 Encoded Version)
IF (IMM8[0] = 0)THEN DEST[63:0] := SRC1[63:0]
ELSE DEST [63:0] := SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] := SRC1[127:64]
ELSE DEST [127:64] := SRC2[127:64] FI
DEST[MAXVL-1:128] := 0




BLENDPD—Blend Packed Double Precision Floating-Point Values                                                                                 Vol. 2A 3-78
VBLENDPD (VEX.256 Encoded Version)
IF (IMM8[0] = 0)THEN DEST[63:0] := SRC1[63:0]
ELSE DEST [63:0] := SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] := SRC1[127:64]
ELSE DEST [127:64] := SRC2[127:64] FI
IF (IMM8[2] = 0) THEN DEST[191:128] := SRC1[191:128]
ELSE DEST [191:128] := SRC2[191:128] FI
IF (IMM8[3] = 0) THEN DEST[255:192] := SRC1[255:192]
ELSE DEST [255:192] := SRC2[255:192] FI

Intel C/C++ Compiler Intrinsic Equivalent

BLENDPD __m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);
VBLENDPD __m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.” BLENDPD—Blend Packed Double Precision Floating-Point Values Vol. 2A 3-79