addps

Add Packed Single-Precision

ADDPS xmm, xmm/m128

Adds four 32-bit floats.

Details

The Add Packed Single-Precision instruction adds four 32-bit floats.

Pseudocode Operation

DEST <- DEST + SRC
// Flags affected: OF, SF, ZF, AF, CF, PF

Example

ADDPS xmm0, xmm1

Encoding

Binary Layout
0F
+0
58
+1
 
Format SSE
Opcode 0F 58
Extension SSE

Operands

  • dest
    128-bit SSE/AVX register (XMM)
  • src
    128-bit XMM register or 128-bit memory