haddpd

Horizontal Add Packed Double-Precision

HADDPD xmm1, xmm2/m128

Adds adjacent double-precision elements horizontally.

Pseudocode Operation

dest[63:0] ← dest[63:0] + dest[127:64];
dest[127:64] ← src[63:0] + src[127:64];

Encoding

Binary Layout
66
+0
0F
+1
7C
+2
 
Format SSE3
Opcode 66 0F 7C
Extension SSE3

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Related

More in SSE3

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
66 0F 7C /r HADDPD xmm1, xmm2/m128 RM V/V SSE3 Horizontal add packed double precision floating-point values from xmm2/m128 to xmm1.
VEX.128.66.0F.WIG 7C /r VHADDPD xmm1,xmm2, xmm3/m128 AVX RVM V/V Horizontal add packed double precision floating-point values from xmm2 and xmm3/mem.
VEX.256.66.0F.WIG 7C /r VHADDPD ymm1, ymm2, ymm3/m256 AVX RVM V/V Horizontal add packed double precision floating-point values from ymm2 and ymm3/mem.

Description

Adds the double precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand. Adds the double precision floating-point values in the high and low quadwords of the source operand and stores the result in the high quadword of the destination operand. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). See Figure 3-12 for HADDPD; see Figure 3-13 for VHADDPD.

HADDPD xmm1, xmm2/m128

xmm2 [127:64] [63:0] /m128

[127:64] [63:0] xmm1

xmm2/m128[63:0] + Result: xmm1[63:0] + xmm1[127:64] xmm2/m128[127:64] xmm1

[127:64] [63:0]

OM15993

SRC1 X3 X2 X1 X0

SRC2 Y3 Y2 Y1 Y0

DEST Y2 + Y3 X2 + X3 Y0 + Y1 X0 + X1

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.

Operation

HADDPD (128-bit Legacy SSE Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]
DEST[127:64] := SRC2[127:64] + SRC2[63:0]
DEST[MAXVL-1:128] (Unmodified)

VHADDPD (VEX.128 Encoded Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]
DEST[127:64] := SRC2[127:64] + SRC2[63:0]
DEST[MAXVL-1:128] := 0

VHADDPD (VEX.256 Encoded Version)
DEST[63:0] := SRC1[127:64] + SRC1[63:0]
DEST[127:64] := SRC2[127:64] + SRC2[63:0]
DEST[191:128] := SRC1[255:192] + SRC1[191:128]
DEST[255:192] := SRC2[255:192] + SRC2[191:128]

Intel C/C++ Compiler Intrinsic Equivalent

VHADDPD __m256d _mm256_hadd_pd (__m256d a, __m256d b);
HADDPD __m128d _mm_hadd_pd (__m128d a, __m128d b);

Exceptions

Other Exceptions

See Table 2-19, “Type 2 Class Exception Conditions.” HADDPD-Packed Double Precision Floating-Point Horizontal Add Vol. 2A 3-435

Numeric Exceptions

Overflow, Underflow, Invalid, Precision, Denormal. HADDPD-Packed Double Precision Floating-Point Horizontal Add Vol. 2A 3-434

Exceptions

When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general- protection exception (#GP) will be generated.