andn

Logical AND NOT

ANDN r32, r32, r/m32

Calculates (NOT src1) AND src2. Non-destructive.

Pseudocode Operation

dest ← (~src1) & src2
ZF ← (dest == 0)
CF ← 0
OF ← 0
AF ← undefined
PF ← undefined

Example

ANDN eax, eax, ebx

Encoding

Binary Layout

VEX

opcode

ModRM

Format VEX

Opcode VEX.LZ.0F38.W0 F2 /r

Extension BMI1

Operands

dest
32-bit general-purpose register (e.g. EAX)
src1
32-bit general-purpose register (e.g. EAX)
src2
32-bit register or memory

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.LZ.0F38.W0 F2 /r	ANDN r32a, r32b, r/m32	RVM	V/V	BMI1 RVM BMI1	Bitwise AND of inverted r32b with r/m32, store result in r32a. VEX.LZ. 0F38.W1 F2 /r V/N.E. Bitwise AND of inverted r64b with r/m64, store result in r64a. ANDN r64a, r64b, r/m64

Description

Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the second source operand). The result is stored in the first operand (destination operand). This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

DEST := (NOT SRC1) bitwiseAND SRC2;
SF := DEST[OperandSize -1];
ZF := (DEST = 0);

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language.

Flags Affected

SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” ANDN-Logical AND NOT Vol. 2A 3-62