tzmsk

Mask From Trailing Zeros

TZMSK r32, r/m32

Creates mask from trailing zeros (~x & (x-1)).

Details

Creates a mask from trailing zeros by computing ~src & (src - 1), isolating only the trailing zero bits. This TBM instruction operates on 32-bit operands in protected/64-bit modes and does not modify any CPU flags.

Pseudocode Operation

dest ← ~src & (src - 1)

Example

TZMSK eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format TBM
Opcode XOP.L0.09.W0 01 /4
Extension TBM

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.09 0.dest.0.00 01 /4 TZMSK reg32, reg/mem32
8F RXB.09 1.dest.0.00 01 /4 TZMSK reg64, reg/mem64

Description

Finds the least significant one bit in the source operand, sets all bits below that bit to 1, clears all other bits to 0 (including the found bit) and writes the result to the destination. If the least significant bit of the source operand is 1, the destination is written with all zeros. This instruction has two operands: TZMSK dest, src In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported. The destination (dest) is a general purpose register. The source operand (src) is a general purpose register or a memory operand. The TZMSK instruction effectively performs a bit-wise logical and of the negation of the source operand and the result of subtracting 1 from the source operand, and stores the result to the destination register: sub tmp1, src, 1 not tmp2, src and dest, tmp1, tmp2 The value of the carry flag of rFLAGs is generated by the sub pseudo-instruction and the remaining arithmetic flags are generated by the and pseudo-instruction. The TZMSK instruction is a TBM instruction. Support for this instruction is indicated by CPUID Fn8000_0001_ECX[TBM] = 1. For more information on using the CPUID instruction, see the instruction reference page for the CPUID instruction on page 165. For a description of all feature flags related to instruction subset support, see Appendix D, “Instruction Subsets and CPUID Feature Flags,” on page 593.