vphaddbq
Vector Packed Horizontal Add Byte to Quadword
VPHADDBQ xmm1, xmm2/m128
Adds adjacent bytes to quadwords.
Details
Horizontally adds all eight signed 8-bit bytes from xmm2/m128 (lower half) and (upper half separately), accumulating results as 64-bit quadwords in xmm1. All bytes from each half are summed to produce two 64-bit results. This XOP extension instruction does not affect EFLAGS and performs signed arithmetic.
Pseudocode Operation
xmm1[63:0] ← sign_extend(xmm2/m128[7:0]) + sign_extend(xmm2/m128[15:8]) + sign_extend(xmm2/m128[23:16]) + sign_extend(xmm2/m128[31:24]) + sign_extend(xmm2/m128[39:32]) + sign_extend(xmm2/m128[47:40]) + sign_extend(xmm2/m128[55:48]) + sign_extend(xmm2/m128[63:56])
xmm1[127:64] ← sign_extend(xmm2/m128[71:64]) + sign_extend(xmm2/m128[79:72]) + sign_extend(xmm2/m128[87:80]) + sign_extend(xmm2/m128[95:88]) + sign_extend(xmm2/m128[103:96]) + sign_extend(xmm2/m128[111:104]) + sign_extend(xmm2/m128[119:112]) + sign_extend(xmm2/m128[127:120])Example
VPHADDBQ xmm1, xmm2/m128
Encoding
Binary Layout
VEX
+0
opcode
+3
ModRM
+4
Operands
-
dest
128-bit XMM SIMD register -
src
128-bit XMM SIMD register or Memory operand
Reference (AMD APM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 8F RXB.09 0.1111.0.00 C3 /r | VPHADDBQ xmm1, xmm2/mem128 |
Description
Signed Byte to Signed Quadword
Adds two sets of eight 8-bit signed integer values of the source and packs the sign-extended sums into the corresponding quadword of the destination.
There are two operands: VPHADDBQ dest, src
The destination is an XMM register and the source is either an XMM register or a 128-bit memory location. Bits [255:128] of the corresponding YMM register are cleared.
Flags Affected
None None
Exceptions
Exceptions
Mode
Exception Cause of Exception
Real Virt Prot
X Instruction not supported, as indicated by CPUID feature identifier.
X X XOP instructions are only recognized in protected mode.
X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE].
X XFEATURE_ENABLED_MASK[2:1] ! = 11b.
Invalid opcode, #UD X XOP.W = 1.
A XOP.vvvv ! = 1111b.
X XOP.L = 1.
X REX, F2, F3, or 66 prefix preceding XOP prefix.
X Lock prefix (F0h) preceding opcode.
Device not available, #NM X CR0.TS = 1.
Stack, #SS X Memory address exceeding stack segment limit or non-canonical.
X Memory address exceeding data segment limit or non-canonical.
General protection, #GP
X Null data segment used to reference memory.
Page fault, #PF X Instruction execution caused a page fault.
Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled.
X — XOP exception
764 [AMDVPHADDBQPublic Use] Instruction Reference