vcvtpd2udq
Convert Packed Double to Unsigned Doubleword
Converts 64-bit doubles to unsigned 32-bit integers.
Pseudocode Operation
for i ← 0 to 7
if k1[i] or no mask:
ymm1[32*i:32*i+31] ← convert_pd_to_udq_saturate(zmm2_or_mem[64*i:64*i+63])
else if zeroing:
ymm1[32*i:32*i+31] ← 0Example
Encoding
Operands
-
dest
256-bit YMM AVX register -
src
512-bit ZMM AVX-512 register or Memory operand
Related
More in AVX-512F
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.128.0F.W1 79 /r | VCVTPD2UDQ xmm1 {k1}{z}, xmm2/m128/m64bcst | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Convert two packed double precision floating-point values in xmm2/m128/m64bcst to two unsigned doubleword integers in xmm1 subject to writemask k1. |
| EVEX.256.0F.W1 79 /r | VCVTPD2UDQ xmm1 {k1}{z}, ymm2/m256/m64bcst | A | V/V | (AVX512VL AND AVX512F) OR AVX10.1 | Convert four packed double precision floating-point values in ymm2/m256/m64bcst to four unsigned doubleword integers in xmm1 subject to writemask k1. |
| EVEX.512.0F.W1 79 /r | VCVTPD2UDQ ymm1 {k1}{z}, zmm2/m512/m64bcst {er} | A | V/V | AVX512F OR AVX10.1 | Convert eight packed double precision floating-point values in zmm2/m512/m64bcst to eight unsigned doubleword integers in ymm1 subject to writemask k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Description
Converts packed double precision floating-point values in the source operand (the second operand) to packed unsigned doubleword integers in the destination operand (the first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value FFFFFFFFH is returned. The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2UDQ (EVEX Encoded Versions) When SRC2 Operand is a Register (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0 VCVTPD2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]) ELSE DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a); VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a); VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a); VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r); VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r); VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r); VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a); VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a); VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a); VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);