tpause
Timed Pause
TPAUSE r32
Pauses execution for a specified time or until trigger.
Details
Pauses execution for a specified time interval (in TSC cycles) or until an external interrupt/event occurs, whichever comes first. The pause duration is specified in EDX:EAX and source operand controls pause type. This instruction requires WAITPKG support and operates only in protected/64-bit modes. No flags are modified; EAX contains a status code on completion.
Pseudocode Operation
if (WAITPKG not supported) raise #UD;
pause_type ← r32 & 0xF;
duration ← EDX:EAX;
if (pause_type == 0) {
// Absolute TSC deadline
while (current_tsc < duration && no_interrupt) pause_cycle();
} else if (pause_type == 1) {
// Relative delay
end_time ← current_tsc + duration;
while (current_tsc < end_time && no_interrupt) pause_cycle();
}
EAX ← status_code;Example
TPAUSE eax
Encoding
Binary Layout
66
+0
0F
+1
AE
+2
ModRM
+3
Operands
-
dest
32-bit general-purpose register (e.g. EAX)
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F AE /6 | TPAUSE r32, <edx>, <eax> | A | V/V | WAITPKG A | Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Instruction Operand Encoding1 Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4 N/A ModRM:r/m (r) N/A N/A N/A |
Description
TPAUSE instructs the processor to enter an implementation-dependent optimized state. There are two such optimized states to choose from: light-weight power/performance optimized state, and improved power/performance optimized state. The selection between the two is governed by the explicit input register bit[0] source operand.
TPAUSE is available when CPUID.07H.00H:ECX.WAITPKG[5] is enumerated as 1. TPAUSE may be executed at any privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.
Unlike PAUSE, the TPAUSE instruction will not cause an abort when used inside a transactional region, described in the chapter Chapter 16, “Programming with Intel® AVX10,” of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 1.
The input register contains information such as the preferred optimized state the processor should enter as described in the following table. Bits other than bit 0 are reserved and will result in #GP if non-zero.
Table 4-23. TPAUSE Input Register Bit Definitions
Bit Value State Name Wakeup Time Power Savings Other Benefits bit[0] = 0 C0.2 Slower Larger Improves performance of the other SMT thread(s) on the same core.
bit[0] = 1 C0.1 Faster Smaller N/A bits[31:1] N/A N/A N/A Reserved
The instruction execution wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value.
Prior to executing the TPAUSE instruction, an operating system may specify the maximum delay it allows the processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32-bit MSR (IA32_UMWAIT_CONTROL at MSR index E1H):
• IA32_UMWAIT_CONTROL[31:2] — Determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value where the upper 30 bits come from this field and the lower two bits are zero.
• IA32_UMWAIT_CONTROL[1] — Reserved.
• IA32_UMWAIT_CONTROL[0] — C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to
C0.1.
If the processor that executed a TPAUSE instruction wakes due to the expiration of the operating system time-limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.
The following additional events cause the processor to exit the implementation-dependent optimized state: a store to the read-set range within the transactional region, an NMI or SMI, a debug exception, a machine check exception, the BINIT# signal, the INIT# signal, and the RESET# signal.
1. The Mod field of the ModR/M byte must have value 11B.
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Other implementation-dependent events may cause the processor to exit the implementation-dependent optimized state proceeding to the instruction following TPAUSE. In addition, an external interrupt causes the processor to exit the implementation-dependent optimized state regardless of whether maskable-interrupts are inhibited (EFLAGS.IF =0). It should be noted that if maskable-interrupts are inhibited execution will proceed to the instruction following TPAUSE.
Operation
os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2) instr_deadline := UINT64(EDX:EAX) IF os_deadline < instr_deadline: deadline := os_deadline using_os_deadline := 1 ELSE: deadline := instr_deadline using_os_deadline := 0 WHILE TSC < deadline: implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0]) IF using_os_deadline AND TSC ≥ deadline: RFLAGS.CF := 1 ELSE: RFLAGS.CF := 0 RFLAGS.AF,PF,SF,ZF,OF := 0
Intel C/C++ Compiler Intrinsic Equivalent
TPAUSE uint8_t _tpause(uint32_t control, uint64_t counter);
Exceptions
Numeric Exceptions
None.
Exceptions (All Operating Modes)
#GP(0) If src[31:1] != 0.
If CR4.TSD = 1 and CPL != 0.
#UD If CPUID.07H.00H:ECX.WAITPKG[5]=0.
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