vzeroall

Zero All YMM Registers

VZEROALL

Clears all YMM registers.

Details

Clears all bits of all 16 YMM registers (YMM0–YMM15 in 64-bit mode, YMM0–YMM7 in 32-bit mode) to zero. This is a faster alternative to clearing individual YMM registers via multiple VXORPS or similar instructions. No flags are affected. Execution is restricted to protected or 64-bit mode.

Pseudocode Operation

for i from 0 to (is_64bit_mode ? 15 : 7) {
  YMM[i][0:255] ← 0;
}

Example

VZEROALL

Encoding

Binary Layout

VEX

Format VEX

Opcode VEX.256.0F.WIG 77

Extension AVX

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.256.0F.WIG 77	VZEROALL	ZO	V/V	AVX	Zero some of the XMM, YMM, and ZMM registers.

Description

In 64-bit mode, the instruction zeroes XMM0-XMM15, YMM0-YMM15, and ZMM0-ZMM15. Outside 64-bit mode, it zeroes only XMM0-XMM7, YMM0-YMM7, and ZMM0-ZMM7. VZEROALL does not modify ZMM16-ZMM31. Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm
registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,
ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. On a machine
supporting Intel AVX-512, the width is 512.

VZEROALL (VEX.256 encoded version)
IF (64-bit mode)
limit :=15
ELSE
limit := 7
FOR i in 0 .. limit:
simd_reg_file[i][MAXVL-1:0] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROALL:      _mm256_zeroall()

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.” VZEROALL—Zero XMM, YMM, and ZMM Registers Vol. 2C 5-775