div

Unsigned Divide

DIV r/m

Unsigned divide (AX / src).

Details

Performs unsigned division of accumulator (AX/DX:AX/EDX:EAX/RDX:RAX) by operand, storing quotient in AL/AX/EAX/RAX and remainder in AH/DX/EDX/RDX respectively. All flags undefined after division. Raises #DE exception if divisor is zero or quotient overflows.

Pseudocode Operation

if (operand_width == 8) { quotient ← AX / src; remainder ← AX mod src; AL ← quotient; AH ← remainder; } else if (operand_width == 16) { quotient ← DX:AX / src; remainder ← DX:AX mod src; AX ← quotient; DX ← remainder; } else if (operand_width == 32) { quotient ← EDX:EAX / src; remainder ← EDX:EAX mod src; EAX ← quotient; EDX ← remainder; } else { quotient ← RDX:RAX / src; remainder ← RDX:RAX mod src; RAX ← quotient; RDX ← remainder; }

Example

DIV rbx

Encoding

Binary Layout

ModRM

Format Legacy

Opcode F7 /6

Extension Base

Operands

dest
Register or memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	Description
F6 /6	DIV r/m8	M	Valid Valid	Unsigned divide AX by r/m8, with result stored in AL := Quotient, AH := Remainder.
F7 /6	DIV r/m16	M	Valid Valid	Unsigned divide DX:AX by r/m16, with result stored in AX := Quotient, DX := Remainder.
F7 /6	DIV r/m32	M	Valid Valid	Unsigned divide EDX:EAX by r/m32, with result stored in EAX := Quotient, EDX := Remainder.
REX.W + F7 /6	DIV r/m64	M	Valid N.E.	Unsigned divide RDX:RAX by r/m64, with result stored in RAX := Quotient, RDX := Remainder.

Description

Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor). Division using 64-bit operand is available only in 64-bit mode. Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag. In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in RAX, the remainder in RDX. See the summary chart at the beginning of this section for encoding data and limits. See Table 3-17. Table 3-17. DIV Action Maximum Operand Size Dividend Divisor Quotient Remainder Quotient Word/byte AX r/m8 AL AH 255 Doubleword/word DX:AX r/m16 AX DX 65,535 Quadword/doubleword EDX:EAX r/m32 EAX EDX 232 − 1 Doublequadword/ RDX:RAX r/m64 RAX RDX 264 − 1 quadword DIV—Unsigned Divide Vol. 2A 3-264

Operation

IF SRC = 0
THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)
THEN
temp := AX / SRC;
IF temp > FFH
THEN #DE; (* Divide error *)
ELSE
AL := temp;
AH := AX MOD SRC;
FI;
ELSE IF OperandSize = 16 (* Doubleword/word operation *)
THEN
temp := DX:AX / SRC;
IF temp > FFFFH
THEN #DE; (* Divide error *)
ELSE
AX := temp;
DX := DX:AX MOD SRC;
FI;
FI;
ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
THEN
temp := EDX:EAX / SRC;
IF temp > FFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
EAX := temp;
EDX := EDX:EAX MOD SRC;
FI;
FI;
ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
THEN
temp := RDX:RAX / SRC;
IF temp > FFFFFFFFFFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
RAX := temp;
RDX := RDX:RAX MOD SRC;
FI;
FI;
FI;

Flags Affected

The CF, OF, SF, ZF, AF, and PF flags are undefined. DIV—Unsigned Divide Vol. 2A 3-265

Exceptions

Protected Mode Exceptions

#DE If the source operand (divisor) is 0 If the quotient is too large for the designated register. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

#DE If the source operand (divisor) is 0. If the quotient is too large for the designated register. #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#DE If the source operand (divisor) is 0. If the quotient is too large for the designated register. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form. #GP(0) If the memory address is in a non-canonical form. #DE If the source operand (divisor) is 0 If the quotient is too large for the designated register. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. DIV—Unsigned Divide Vol. 2A 3-266